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@ -6,6 +6,7 @@
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# All rights reserved.
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#
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# This file aiming to create the sram module without routing
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# provide methods of seperated lef file generation
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import datetime
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from math import ceil
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from importlib import import_module, reload
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@ -253,35 +254,7 @@ class sram_1bank(design, verilog, lef):
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design=self)
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pl.add_io_pins(pins_to_route)
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#pl.design.remove_layout_pin("wmask0[0]") # this could use for deleting pins
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'''
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# add the corresponding pin to the edge, the io pin will be put defaut as the nearest edge
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for pin_name in pins_to_route:
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ll, ur = bbox
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pin = self.get_pin(pin_name)
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print(pin)
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c = pin.center()
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# Find the closest edge
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edge, vertical = self.get_closest_edge(c,bbox=bbox)
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# Keep the fake pin out of the SRAM layout are so that they won't be
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# blocked by previous signals if they're on the same orthogonal line
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if edge == "left":
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fake_center = vector(ll.x - rtr.track_wire * 2, c.y)
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if edge == "bottom":
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fake_center = vector(c.x, ll.y - rtr.track_wire * 2)
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if edge == "right":
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fake_center = vector(ur.x + rtr.track_wire * 2, c.y)
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if edge == "top":
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fake_center = vector(c.x, ur.y + rtr.track_wire * 2)
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# Create the fake pin shape
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layer = rtr.get_layer(int(not vertical))
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self.add_layout_pin_rect_center(text=pin_name + "_IO",
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layer=layer,
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offset=fake_center)
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rtr.add_perimeter_fake_pins()
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'''
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def get_closest_edge(self, point, bbox):
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""" Return a point's the closest edge and the edge's axis direction. """
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@ -109,7 +109,7 @@ class io_pin_placer(router):
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fake_center = vector(c.x + add_distance, ur.y + self.track_wire * 2 - offset)
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is_too_close = any(abs(pin_added.center().x - fake_center.x) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_up)
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# Create the fake pin shape
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# Create the fake pin shape, here make sure the pin in the gds will be big enough
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layer = self.get_layer(int(not vertical))
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half_wire_vector = vector([self.half_wire] * 2)
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nll = fake_center - half_wire_vector - half_wire_vector
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@ -162,7 +162,7 @@ class sram():
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spname = OPTS.output_path + self.s.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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#''' #comment the following state when generating big sram, and then disable drc/lvs, because maigc_ext stuck
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''' #comment the following state when generating big sram, and then disable drc/lvs, because maigc_ext stuck
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# Save a functional simulation file with default period
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functional(self.s,
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spname,
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@ -184,7 +184,7 @@ class sram():
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d.targ_write_ports = [self.s.write_ports[0]]
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d.write_delay_stimulus()
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print_time("DELAY", datetime.datetime.now(), start_time)
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#''' #comment the above when generating big sram, and then disable drc/;vs, bevause magic_ext stuck
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''' #comment the above when generating big sram, and then disable drc/lvs, bevause magic_ext stuck
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# Save trimmed spice file
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temp_trim_sp = "{0}trimmed.sp".format(OPTS.output_path)
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self.sp_write(temp_trim_sp, lvs=False, trim=True)
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@ -66,7 +66,8 @@ class sram():
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self.name = name
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#from openram.modules.sram_1bank import sram_1bank as sram
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from openram.modules.sram_part import sram_1bank as sram
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from openram.modules.sram_for_road import sram_for_road as sram
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self.s = sram(name, sram_config)
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def get_sp_name(self):
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@ -77,6 +77,9 @@ s = sram()
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s.save()
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#s.save_only()
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'''
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from openram import sram_road
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s = sram_road.sram(mod=0)
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s.save(mod=0)
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del s
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s = sram_road.sram(mod=1)
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s.save(mod=1)
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