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This commit is contained in:
FriedrichWu 2024-09-17 11:54:30 +02:00
parent 20e454925a
commit ee6be23cfa
6 changed files with 2387 additions and 32 deletions

File diff suppressed because it is too large Load Diff

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@ -6,6 +6,7 @@
# All rights reserved.
#
# This file aiming to create the sram module without routing
# provide methods of seperated lef file generation
import datetime
from math import ceil
from importlib import import_module, reload
@ -253,35 +254,7 @@ class sram_1bank(design, verilog, lef):
design=self)
pl.add_io_pins(pins_to_route)
#pl.design.remove_layout_pin("wmask0[0]") # this could use for deleting pins
'''
# add the corresponding pin to the edge, the io pin will be put defaut as the nearest edge
for pin_name in pins_to_route:
ll, ur = bbox
pin = self.get_pin(pin_name)
print(pin)
c = pin.center()
# Find the closest edge
edge, vertical = self.get_closest_edge(c,bbox=bbox)
# Keep the fake pin out of the SRAM layout are so that they won't be
# blocked by previous signals if they're on the same orthogonal line
if edge == "left":
fake_center = vector(ll.x - rtr.track_wire * 2, c.y)
if edge == "bottom":
fake_center = vector(c.x, ll.y - rtr.track_wire * 2)
if edge == "right":
fake_center = vector(ur.x + rtr.track_wire * 2, c.y)
if edge == "top":
fake_center = vector(c.x, ur.y + rtr.track_wire * 2)
# Create the fake pin shape
layer = rtr.get_layer(int(not vertical))
self.add_layout_pin_rect_center(text=pin_name + "_IO",
layer=layer,
offset=fake_center)
rtr.add_perimeter_fake_pins()
'''
def get_closest_edge(self, point, bbox):
""" Return a point's the closest edge and the edge's axis direction. """

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@ -109,7 +109,7 @@ class io_pin_placer(router):
fake_center = vector(c.x + add_distance, ur.y + self.track_wire * 2 - offset)
is_too_close = any(abs(pin_added.center().x - fake_center.x) < (0.8 + self.half_wire * 4)for pin_added in self.io_pins_added_up)
# Create the fake pin shape
# Create the fake pin shape, here make sure the pin in the gds will be big enough
layer = self.get_layer(int(not vertical))
half_wire_vector = vector([self.half_wire] * 2)
nll = fake_center - half_wire_vector - half_wire_vector

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@ -162,7 +162,7 @@ class sram():
spname = OPTS.output_path + self.s.name + ".sp"
debug.print_raw("SP: Writing to {0}".format(spname))
self.sp_write(spname)
#''' #comment the following state when generating big sram, and then disable drc/lvs, because maigc_ext stuck
''' #comment the following state when generating big sram, and then disable drc/lvs, because maigc_ext stuck
# Save a functional simulation file with default period
functional(self.s,
spname,
@ -184,7 +184,7 @@ class sram():
d.targ_write_ports = [self.s.write_ports[0]]
d.write_delay_stimulus()
print_time("DELAY", datetime.datetime.now(), start_time)
#''' #comment the above when generating big sram, and then disable drc/;vs, bevause magic_ext stuck
''' #comment the above when generating big sram, and then disable drc/lvs, bevause magic_ext stuck
# Save trimmed spice file
temp_trim_sp = "{0}trimmed.sp".format(OPTS.output_path)
self.sp_write(temp_trim_sp, lvs=False, trim=True)

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@ -66,7 +66,8 @@ class sram():
self.name = name
#from openram.modules.sram_1bank import sram_1bank as sram
from openram.modules.sram_part import sram_1bank as sram
from openram.modules.sram_for_road import sram_for_road as sram
self.s = sram(name, sram_config)
def get_sp_name(self):

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@ -77,6 +77,9 @@ s = sram()
s.save()
#s.save_only()
'''
from openram import sram_road
s = sram_road.sram(mod=0)
s.save(mod=0)
del s
s = sram_road.sram(mod=1)
s.save(mod=1)