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Fix sky130 1rw LVS mismatch by correcting col_cap pin order

This commit is contained in:
rlin50 2026-02-22 22:11:35 -08:00
parent ea15a81443
commit ec28bc6dfd
2 changed files with 11 additions and 10 deletions
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9
technology/sky130/custom/sky130_bitcell_base_array.py
View File

@ -100,14 +100,15 @@ class sky130_bitcell_base_array(bitcell_base_array):
strap_pins = []
for port in self.all_ports:
strap_pins.extend([x for x in self.get_bitline_names(port) if "bl" in x and x.endswith("_{0}".format(col))])
strap_pins.extend(["vdd", "gnd"])
for port in self.all_ports:
strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
# col_cap_1port_bitcell port order:
# [bl, br, vdd, gnd, vpb, vnb, gate]
strap_pins.extend(["vdd", "gnd", "vdd", "gnd"])
if row == 0:
strap_pins.extend(["top_gate"])
strap_pins.append("top_gate")
else:
strap_pins.extend(["bot_gate"])
strap_pins.extend(["vdd", "gnd"])
strap_pins.append("bot_gate")
return strap_pins
def get_row_cap_pins(self, row, col):

12
technology/sky130/custom/sky130_col_cap_array.py
View File

@ -75,12 +75,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
row_layout.append(self.colend1)
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
pins.append("fake_bl_{}".format(bitline))
pins.append("vdd")
pins.append("gnd")
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
pins.append("vdd")
pins.append("gnd")
pins.append("vdd")
pins.append("gnd")
pins.append("gate")
bitline += 1
elif col % 4 == 1:
row_layout.append(self.colend2)
@ -92,12 +92,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
row_layout.append(self.colend1)
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
pins.append("fake_bl_{}".format(bitline))
pins.append("vdd")
pins.append("gnd")
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
pins.append("vdd")
pins.append("gnd")
pins.append("vdd")
pins.append("gnd")
pins.append("gate")
bitline += 1
elif col % 4 ==3:
row_layout.append(self.colend2)