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fix col_cap array for dummu compatability ...bitcells next

This commit is contained in:
Jesse Cirimelli-Low 2025-03-06 02:05:43 -08:00
parent f3c1c5fbb2
commit 4ce6e0538b
7 changed files with 32 additions and 19 deletions
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3
Makefile
View File

@ -13,8 +13,7 @@ SRAM_LIB_GIT_REPO ?= https://github.com/vlsida/sky130_fd_bd_sram.git
# Use this for development
#SRAM_LIB_GIT_REPO ?= git@github.com:VLSIDA/sky130_fd_bd_sram.git
#SRAM_LIB_GIT_REPO ?= https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
SRAM_LIB_GIT_COMMIT ?= 8dccd8d8ddb0a9de1b02207b2cd0c0d697807aa9
SRAM_LIB_GIT_COMMIT ?= 9bb620d12ae380dfe38f9a68df809f068f7b2a21
SKY130_PDK ?= $(PDK_ROOT)/sky130A
GF180_PDK ?= $(PDK_ROOT)/gf180mcuD

8
compiler/modules/capped_replica_bitcell_array.py
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@ -87,7 +87,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
# dummy column + left replica column(s)
column_offset=0,
mirror=0,
location="top")
location="top",
left_rbl=self.left_rbl,
right_rbl=self.right_rbl)
self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
cols=self.column_size + len(self.rbls),
@ -95,7 +97,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
# dummy column + left replica column(s)
column_offset=0,
mirror=0,
location="bottom")
location="bottom",
left_rbl=self.left_rbl,
right_rbl=self.right_rbl)
# Dummy Col or Row Cap, depending on bitcell array properties
row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")

2
compiler/modules/col_cap_array.py
View File

@ -12,7 +12,7 @@ class col_cap_array(bitcell_base_array):
"""
Generate a dummy row/column for the replica array.
"""
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="",left_rbl=[],right_rbl=[]):
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
self.mirror = mirror
self.location = location

3
compiler/modules/pattern.py
View File

@ -176,9 +176,6 @@ class pattern():
self.parent_design.all_inst[row, col] = self.parent_design.add_existing_inst(inst,self.name_template.format(row, col))
self.parent_design.connect_inst(self.parent_design.get_strap_pins(self.bit_rows[col], self.bit_cols[row]))
def print_bit_blocck():
return
def place_inst(self, inst, offset) -> None:
x = offset[0]
y = offset[1]

21
technology/sky130/custom/sky130_col_cap.py
View File

@ -8,20 +8,29 @@
from openram import debug
from openram.base import design
from openram.tech import cell_properties as props
from openram import OPTS
class sky130_col_cap(design):
def __init__(self, version, name=""):
def __init__(self, version, name="",left_rbl=[],right_rbl=[]):
if version == "colend":
cell_name = "sky130_fd_bd_sram__sram_sp_colend"
if OPTS.control_logic == "control_logic_delay" or not right_rbl:
cell_name = "sky130_fd_bd_sram__sram_sp_colend"
else:
cell_name = "sky130_fd_bd_sram__openram_sp_colend_replica"
prop = props.col_cap_1port_bitcell
elif version == "colenda":
if OPTS.control_logic == "control_logic_delay" or not left_rbl:
cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
else:
cell_name = "sky130_fd_bd_sram__openram_sp_colenda_replica"
prop = props.col_cap_1port_bitcell
elif version == "colend_p_cent":
cell_name = "sky130_fd_bd_sram__sram_sp_colend_p_cent"
prop = props.col_cap_1port_strap_ground
elif version == "colenda":
cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
prop = props.col_cap_1port_bitcell
elif version == "colenda_p_cent":
cell_name = "sky130_fd_bd_sram__sram_sp_colenda_p_cent"
prop = props.col_cap_1port_strap_ground

10
technology/sky130/custom/sky130_col_cap_array.py
View File

@ -18,18 +18,20 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
"""
Generate a dummy row/column for the replica array.
"""
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name=""):
super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name)
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="", left_rbl=[],right_rbl=[]):
self.left_rbl = left_rbl
self.right_rbl = right_rbl
super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name, left_rbl=left_rbl, right_rbl=right_rbl)
self.no_instances = False
def add_modules(self):
""" Add the modules used in this design """
if self.location == "top":
self.colend1 = factory.create(module_type="col_cap", version="colend")
self.colend1 = factory.create(module_type="col_cap", version="colend",left_rbl=self.left_rbl, right_rbl=self.right_rbl)
self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent")
self.colend3 = factory.create(module_type="col_cap", version="colend_cent")
elif self.location == "bottom":
self.colend1 = factory.create(module_type="col_cap", version="colenda")
self.colend1 = factory.create(module_type="col_cap", version="colenda",left_rbl=self.left_rbl, right_rbl=self.right_rbl)
self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent")
self.colend3 = factory.create(module_type="col_cap", version="colenda_cent")

4
technology/sky130/tech/tech.py
View File

@ -814,7 +814,9 @@ flatglob = ["*_?mos_m*",
blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
"sky130_fd_bd_sram__openram_dp_cell_dummy",
"sky130_fd_bd_sram__openram_dp_cell_replica",
"sky130_fd_bd_sram__openram_sp_colend_replica",
"sky130_fd_bd_sram__openram_sp_colenda_replica",
"sky130_fd_bd_sram__sram_sp_cell_opt1a",
"sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy",
"sky130_fd_bd_sram__openram_sp_cell_opt1_dummy",