 Matt Guthaus
|
90d1fa7c43
|
Bitcell supply routing fixes.
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
|
2018-11-30 12:32:13 -08:00 |
|
|
Matt Guthaus
|
7e054a51e2
|
Some techs don't need m1 power pins
|
2018-11-29 18:47:38 -08:00 |
|
|
Matt Guthaus
|
0af4263edb
|
Remove extra rotated vias in bitcell array to simplify power routing
|
2018-11-29 18:13:15 -08:00 |
|
 Matt Guthaus
|
33a7683473
|
Remove used gated_clk instead of cs for read-only control logic.
|
2018-11-29 16:28:37 -08:00 |
|
|
Matt Guthaus
|
3c4d559308
|
Fixed syntax error referring to column mux
|
2018-11-29 13:29:16 -08:00 |
|
|
Matt Guthaus
|
3d3f54aa86
|
Add col addr line spacing for col addr decoder
|
2018-11-29 13:22:48 -08:00 |
|
|
Matt Guthaus
|
4df862d8af
|
Convert channel router to take netlist of pins rather than names.
|
2018-11-29 12:12:10 -08:00 |
|
|
Matt Guthaus
|
7054d0881a
|
Fix col address dff spacing from bank.
|
2018-11-29 09:54:29 -08:00 |
|
|
Matt Guthaus
|
02a67f9867
|
Missing gap in port 1 col decoder
|
2018-11-28 18:07:31 -08:00 |
|
|
Matt Guthaus
|
d041a498f3
|
Fix height of port 1 control bus. Adjust column decoder names.
|
2018-11-28 17:48:25 -08:00 |
|
|
Matt Guthaus
|
a2a9cea37e
|
Make column decoder same height as control to control and supply overlaps
|
2018-11-28 16:59:58 -08:00 |
|
|
Matt Guthaus
|
d99dcd33e2
|
Fix SRAM level control routing errors.
|
2018-11-28 15:30:52 -08:00 |
|
|
Matt Guthaus
|
143e4ed7f9
|
Change hierchical decoder output order to match changes to netlist.
|
2018-11-28 14:09:45 -08:00 |
|
|
Matt Guthaus
|
b5b691b73d
|
Fix missing via in clk input of control
|
2018-11-28 13:20:39 -08:00 |
|
|
Matt Guthaus
|
2ed8fc1506
|
pgate inputs and outputs are all on M1 for flexible via placement when using gates.
|
2018-11-28 12:42:29 -08:00 |
|
|
Matt Guthaus
|
93904d9f2d
|
Control logic passes DRC/LVS in SCMOS
|
2018-11-28 11:02:24 -08:00 |
|
|
Matt Guthaus
|
410115e830
|
Modify dff_buf to stagger Q and Qb outputs.
|
2018-11-28 10:43:11 -08:00 |
|
|
Matt Guthaus
|
25611fcbc1
|
Remove dff_inv since we can just use dff_buf
|
2018-11-28 10:42:22 -08:00 |
|
|
Matt Guthaus
|
ea6abfadb7
|
Stagger outputs of dff_buf
|
2018-11-28 09:48:16 -08:00 |
|
|
Matt Guthaus
|
c43a140b5e
|
All control routed and DRC clean. LVS errors.
|
2018-11-27 17:18:03 -08:00 |
|
|
Matt Guthaus
|
c45f990413
|
Change en to en_bar in precharge. Fix logic for inverted p_en_bar.
|
2018-11-27 14:17:55 -08:00 |
|
|
Matt Guthaus
|
bf31126679
|
Correct decoder output numbers to follow address order
|
2018-11-27 12:03:13 -08:00 |
|
|
Matt Guthaus
|
b912f289a6
|
Remove extra X in instance names
|
2018-11-27 12:02:53 -08:00 |
|
|
Matt Guthaus
|
2237af0463
|
Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix
|
2018-11-26 18:01:34 -08:00 |
|
|
Matt Guthaus
|
cf23eacd0e
|
Add wl_en
|
2018-11-26 18:00:59 -08:00 |
|
|
Matt Guthaus
|
21759d59b4
|
Remove inverter in wordline driver
|
2018-11-26 16:41:31 -08:00 |
|
|
Matt Guthaus
|
9e0b31d685
|
Make pand2 and pbuf derive pgate. Initial DRC wrong layout.
|
2018-11-26 16:19:18 -08:00 |
|
|
Matt Guthaus
|
dd79fc560b
|
Corretct modules for add_inst
|
2018-11-26 15:35:29 -08:00 |
|
|
Matt Guthaus
|
b440031855
|
Add netlist only mode to new pgates
|
2018-11-26 15:29:42 -08:00 |
|
 Hunter Nichols
|
67977bab3e
|
Fixed port issue in bank. Changed golden data due to netlist change.
|
2018-11-20 11:39:14 -08:00 |
|
|
Hunter Nichols
|
62cbbca852
|
Merged, fixed conflict bt matching control logic creation to dev.
|
2018-11-19 22:20:20 -08:00 |
|
|
Hunter Nichols
|
2f29ad5510
|
Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed.
|
2018-11-19 22:13:58 -08:00 |
|
|
Hunter Nichols
|
e8f1c19af6
|
Merge branch 'dev' into multiport_characterization
|
2018-11-19 15:42:48 -08:00 |
|
|
Matt Guthaus
|
a47509de26
|
Move via away from cell edges
|
2018-11-19 15:42:22 -08:00 |
|
|
Hunter Nichols
|
a55d907d03
|
High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME
|
2018-11-19 15:40:26 -08:00 |
|
|
Matt Guthaus
|
4630f52de2
|
Use array ur instead of bank ur to pace row addr dff
|
2018-11-19 08:41:26 -08:00 |
|
|
Hunter Nichols
|
d3c47ac976
|
Made delay measurements less dependent on period.
|
2018-11-18 23:28:49 -08:00 |
|
|
Matt Guthaus
|
ba8bec3f67
|
Two m1 pitches at top of control logic
|
2018-11-18 09:30:27 -08:00 |
|
|
Matt Guthaus
|
c677efa217
|
Fix control logic center location. Fix rail height error in write only control logic.
|
2018-11-18 09:15:03 -08:00 |
|
|
Hunter Nichols
|
3716030a23
|
Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts.
|
2018-11-16 16:57:22 -08:00 |
|
|
Matt Guthaus
|
047d6ca2ef
|
Must channel rout the column mux bits since they could overlap
|
2018-11-16 16:21:31 -08:00 |
|
|
Matt Guthaus
|
b89c011e41
|
Add psram 1w/1r test. Fix bl/br port naming errors in bank.
|
2018-11-16 15:31:22 -08:00 |
|
|
Matt Guthaus
|
ca750b698a
|
Uniquify bitcell array
|
2018-11-16 12:52:22 -08:00 |
|
|
Matt Guthaus
|
5e0eb609da
|
Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
|
2018-11-16 11:48:41 -08:00 |
|
|
Matt Guthaus
|
68ac7e5955
|
Fix offset of column decoder with new mirroring
|
2018-11-15 17:27:58 -08:00 |
|
|
Matt Guthaus
|
712b71c5ca
|
Mirror port 1 column decoder in X and Y
|
2018-11-15 15:26:59 -08:00 |
|
|
Matt Guthaus
|
21d111acfe
|
Move wordline driver clock line below decoder. Fix port 1 clock route DRC.
|
2018-11-15 10:30:38 -08:00 |
|
|
Hunter Nichols
|
6e47de3f9b
|
Separated relative delay into rise/fall.
|
2018-11-14 23:34:53 -08:00 |
|
|
Matt Guthaus
|
3221d3e744
|
Add initial support and unit tests for 2 port SRAM
|
2018-11-14 17:05:23 -08:00 |
|
|
Hunter Nichols
|
e9f6566e59
|
Fixed merge conflict, moved control logic mod instantiation, removed some commented out code.
|
2018-11-14 13:53:27 -08:00 |
|