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bank.py
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All control routed and DRC clean. LVS errors.
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2018-11-27 17:18:03 -08:00 |
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bank_select.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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bitcell_array.py
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Uniquify bitcell array
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2018-11-16 12:52:22 -08:00 |
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control_logic.py
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pgate inputs and outputs are all on M1 for flexible via placement when using gates.
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2018-11-28 12:42:29 -08:00 |
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delay_chain.py
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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dff.py
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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dff_array.py
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Remove extra X in instance names
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2018-11-27 12:02:53 -08:00 |
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dff_buf.py
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Modify dff_buf to stagger Q and Qb outputs.
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2018-11-28 10:43:11 -08:00 |
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dff_buf_array.py
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Remove extra X in instance names
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2018-11-27 12:02:53 -08:00 |
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dff_inv.py
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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hierarchical_decoder.py
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All control routed and DRC clean. LVS errors.
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2018-11-27 17:18:03 -08:00 |
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hierarchical_predecode.py
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Remove extra X in instance names
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2018-11-27 12:02:53 -08:00 |
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hierarchical_predecode2x4.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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hierarchical_predecode3x8.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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multibank.py
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Initial two port bank in SCMOS
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2018-11-13 16:05:22 -08:00 |
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precharge_array.py
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Change en to en_bar in precharge. Fix logic for inverted p_en_bar.
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2018-11-27 14:17:55 -08:00 |
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replica_bitline.py
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Uniquify bitcell array
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2018-11-16 12:52:22 -08:00 |
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sense_amp.py
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Document why sense amp is 8x isolation transistor
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2018-11-07 16:09:50 -08:00 |
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sense_amp_array.py
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Fixed spacing in golden lib files. Added column mux into analytical model.
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2018-10-24 00:16:26 -07:00 |
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single_level_column_mux_array.py
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Change default col mux size to 2. Add some comments.
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2018-11-07 15:43:08 -08:00 |
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tri_gate.py
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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tri_gate_array.py
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Update all drc usages to call function type
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2018-10-12 14:37:51 -07:00 |
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wordline_driver.py
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Remove inverter in wordline driver
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2018-11-26 16:41:31 -08:00 |
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write_driver.py
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Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
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2018-11-07 11:31:44 -08:00 |
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write_driver_array.py
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Remove extra X in instance names
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2018-11-27 12:02:53 -08:00 |
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