Matt Guthaus dd79fc560b Corretct modules for add_inst

2018-11-26 15:35:29 -08:00

..

bank_select.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

bank.py

Use array ur instead of bank ur to pace row addr dff

2018-11-19 08:41:26 -08:00

bitcell_array.py

Uniquify bitcell array

2018-11-16 12:52:22 -08:00

control_logic.py

Corretct modules for add_inst

2018-11-26 15:35:29 -08:00

delay_chain.py

Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.

2018-09-26 19:10:24 -07:00

dff_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_buf_array.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_buf.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_inv_array.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_inv.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

hierarchical_decoder.py

Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.

2018-10-20 12:54:12 -07:00

hierarchical_predecode2x4.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

hierarchical_predecode3x8.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

hierarchical_predecode.py

Move via away from cell edges

2018-11-19 15:42:22 -08:00

multibank.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

precharge_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

replica_bitline.py

Uniquify bitcell array

2018-11-16 12:52:22 -08:00

sense_amp_array.py

Fixed spacing in golden lib files. Added column mux into analytical model.

2018-10-24 00:16:26 -07:00

sense_amp.py

Document why sense amp is 8x isolation transistor

2018-11-07 16:09:50 -08:00

single_level_column_mux_array.py

Change default col mux size to 2. Add some comments.

2018-11-07 15:43:08 -08:00

tri_gate_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

tri_gate.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

wordline_driver.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

write_driver_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

write_driver.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00