Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev.

2018-11-19 22:20:20 -08:00

..

bank_select.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

bank.py

Merged, fixed conflict bt matching control logic creation to dev.

2018-11-19 22:20:20 -08:00

bitcell_array.py

Merge branch 'dev' into multiport_characterization

2018-11-19 15:42:48 -08:00

control_logic.py

Merged, fixed conflict bt matching control logic creation to dev.

2018-11-19 22:20:20 -08:00

delay_chain.py

Separated relative delay into rise/fall.

2018-11-14 23:34:53 -08:00

dff_array.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

dff_buf_array.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_buf.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_inv_array.py

Merge branch 'dev' into multiport_characterization

2018-11-19 15:42:48 -08:00

dff_inv.py

Merge branch 'dev' into multiport_characterization

2018-11-19 15:42:48 -08:00

dff.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

hierarchical_decoder.py

Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.

2018-10-20 12:54:12 -07:00

hierarchical_predecode2x4.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

hierarchical_predecode3x8.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

hierarchical_predecode.py

Move via away from cell edges

2018-11-19 15:42:22 -08:00

multibank.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

precharge_array.py

Added sense amp enable delay calculation.

2018-11-08 23:54:18 -08:00

replica_bitline.py

Merge branch 'dev' into multiport_characterization

2018-11-19 15:42:48 -08:00

sense_amp_array.py

Added sense amp enable delay calculation.

2018-11-08 23:54:18 -08:00

sense_amp.py

Merged with dev. Fixed merge conflict.

2018-11-09 17:18:19 -08:00

single_level_column_mux_array.py

Change default col mux size to 2. Add some comments.

2018-11-07 15:43:08 -08:00

tri_gate_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

tri_gate.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

wordline_driver.py

Separated relative delay into rise/fall.

2018-11-14 23:34:53 -08:00

write_driver_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

write_driver.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00