OpenRAM/compiler/modules
Matt Guthaus ea6abfadb7 Stagger outputs of dff_buf 2018-11-28 09:48:16 -08:00
..
bank.py All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
bank_select.py Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
bitcell_array.py Uniquify bitcell array 2018-11-16 12:52:22 -08:00
control_logic.py All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
delay_chain.py
dff.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
dff_array.py Remove extra X in instance names 2018-11-27 12:02:53 -08:00
dff_buf.py Stagger outputs of dff_buf 2018-11-28 09:48:16 -08:00
dff_buf_array.py Remove extra X in instance names 2018-11-27 12:02:53 -08:00
dff_inv.py Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
dff_inv_array.py Remove extra X in instance names 2018-11-27 12:02:53 -08:00
hierarchical_decoder.py All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
hierarchical_predecode.py Remove extra X in instance names 2018-11-27 12:02:53 -08:00
hierarchical_predecode2x4.py Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
hierarchical_predecode3x8.py Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
multibank.py Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
precharge_array.py Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
replica_bitline.py Uniquify bitcell array 2018-11-16 12:52:22 -08:00
sense_amp.py Document why sense amp is 8x isolation transistor 2018-11-07 16:09:50 -08:00
sense_amp_array.py
single_level_column_mux_array.py Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00
tri_gate.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
tri_gate_array.py
wordline_driver.py Remove inverter in wordline driver 2018-11-26 16:41:31 -08:00
write_driver.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
write_driver_array.py Remove extra X in instance names 2018-11-27 12:02:53 -08:00