mrg
4df02dad67
Move spare wen_dff to the right by spare columns
2020-06-28 14:28:43 -07:00
mrg
0c9f52e22f
Realign col decoder and control by 1/4 so metal can pass over
2020-06-28 07:15:06 -07:00
mrg
66ea559209
Use channel for dffs all at once
2020-06-27 08:23:12 -07:00
mrg
7220b23402
Add riscv unit tests
2020-06-25 15:34:18 -07:00
mrg
52ee7b0a19
Disable perimeter pins and make an option
2020-06-14 16:44:10 -07:00
mrg
78be9f367a
Add brain-dead router pins to perimeter
2020-06-14 15:52:09 -07:00
mrg
8e8a97cc4b
Add correct boundary to SRAM
2020-06-14 14:17:35 -07:00
Aditi Sinha
d5041afebc
Merge branch 'dev' into bisr
2020-06-07 16:27:25 +00:00
mrg
717188f85c
Change L shape of rbl route
2020-06-04 11:03:39 -07:00
Aditi Sinha
eb0c595dbe
SRAM layout and functional tests with spare cols
2020-06-03 12:31:30 +00:00
Aditi Sinha
c7d86b21ae
Spare cols with wmask enabled
2020-05-16 10:09:03 +00:00
Aditi Sinha
8bd1052fc2
Spare columns in full sram layout
2020-05-14 10:30:29 +00:00
Aditi Sinha
a5c211bd90
Merge branch 'dev' into bisr
2020-05-13 22:39:29 +00:00
mrg
b7c66d7e07
Changes to simplify metal preferred directions and pitches.
...
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
2020-05-10 11:32:45 -07:00
jcirimel
0f9e38881c
update stim for large pex layouts
2020-05-04 03:05:33 -07:00
jcirimel
89688f8ea9
fix pex for larger memories
2020-05-04 01:31:51 -07:00
Aditi Sinha
2498ff07ea
Merge branch 'dev' into bisr
2020-05-02 07:48:35 +00:00
Aditi Sinha
2661a42726
changes to support spare columns
2020-04-14 03:09:10 +00:00
mrg
c8c74e8b69
Fix lvs_write in sram class
2020-04-06 15:20:59 -07:00
mrg
f358de78bb
Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
2020-04-03 13:39:54 -07:00
mrg
2850b9efb5
Don't force check in lib characterization. PEP8 formatting.
2020-04-02 12:52:42 -07:00
mrg
9106e22b58
Fix typo and syntax error.
2020-04-02 10:37:21 -07:00
mrg
5349323acd
PEP8 cleanup. DRC/LVS returns errors.
2020-04-02 09:47:39 -07:00
Aditi Sinha
b75eeb7688
Merge branch 'dev' into bisr
2020-03-22 21:58:04 +00:00
Aditi Sinha
a5afbfe0aa
Fixed errors in extra rows characterization
2020-03-22 20:54:49 +00:00
mrg
ee18f61cbf
Route RBL to edge of bank.
2020-03-06 09:03:52 -08:00
mrg
05f9e809b4
PEP8 Formatting
2020-03-05 16:27:35 -08:00
mrg
6506622dfb
PEP8 Formatting
2020-03-05 16:20:21 -08:00
mrg
5b23653369
PEP8 Formatting
2020-03-05 16:13:49 -08:00
Aditi Sinha
34939ebd70
Merge branch 'dev' into bisr
2020-02-20 17:09:09 +00:00
mrg
5928a93772
Merge branch 'dev' into tech_migration
2020-02-10 22:42:50 +00:00
jcirimel
b212b3e85a
s8 gdsless netlist only working up to dff array
2020-02-09 21:37:09 -08:00
mrg
4d85640a00
Change col addr spacing to col addr size
2020-02-07 22:20:16 +00:00
mrg
2ff058f5d5
PEP8 Cleanup and reverse pitch offset of col addr routing
2020-02-06 22:59:30 +00:00
mrg
4b06ab9eaf
Move port 2 column address bus down.
...
PEP 8 cleanup.
2020-02-06 19:46:10 +00:00
Jesse Cirimelli-Low
b107934672
fix styling
2020-02-06 12:15:52 +00:00
Jesse Cirimelli-Low
3a06141030
add simple sram sizing for netlist only
2020-02-06 12:10:49 +00:00
mrg
79391b84da
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
Bastian Koppelmann
9749c522d1
tech: Make power_grid configurable
...
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.
For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.
Signed-off-by: Bastian Koppelmann <[email protected]
2020-01-28 12:06:34 +01:00
Jesse Cirimelli-Low
6e070925b6
update magic for multiport
2020-01-28 02:32:34 +00:00
Jesse Cirimelli-Low
30604fb093
add multiport support for pex labels
2020-01-28 00:28:55 +00:00
Jesse Cirimelli-Low
1a97dfc63e
syncronize bitline naming convention betwen bitcell and pbitcell
2020-01-27 11:50:43 +00:00
Jesse Cirimelli-Low
d42cd9a281
pbitcell working with bitline adjustments
2020-01-27 10:03:31 +00:00
Jesse Cirimelli-Low
1062cbfd7f
begin fixes to pbitcell, prepare multibank pex
2020-01-24 10:24:29 +00:00
jcirimel
40c01dab85
fix bl in stim file
2020-01-21 01:44:15 -08:00
jcirimel
73691f6054
fix bug in top level bitline label placement
2020-01-21 00:20:52 -08:00
Jesse Cirimelli-Low
5778901cfe
pull bitline labels to top level spice
2020-01-20 12:16:30 +00:00
jcirimel
364842569a
fix s_en in stim
2020-01-16 12:16:49 -08:00
jcirimel
075bf0d841
label bitcell in stim, add s_en top level to stim
2020-01-16 03:51:29 -08:00
Jesse Cirimelli-Low
3ab99d7f9c
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
mrg
Aditi Sinha
jcirimel
Bastian Koppelmann