mrg
dcd29214bc
Temp fix to use old device names during Calibre LVS.
2020-10-21 17:05:48 -07:00
mrg
af40f3077c
Change sky130 device cards to start with X
2020-10-15 13:56:10 -07:00
mrg
ca2ce8b070
Default bitcell opt1
2020-10-12 17:08:32 -07:00
jcirimel
4a1a7e637e
merge in dev
2020-10-07 11:54:07 -07:00
jcirimel
888646cdf9
merge in wlbuf and begin work on 32kb memory
2020-10-06 05:03:59 -07:00
mrg
4a58f09c1c
Use 4x16 decoder with dual port bitcell in tests.
2020-10-05 10:52:56 -07:00
mrg
c06b02e6fc
Rename single_level_column_mux to just column_mux
2020-10-05 08:56:51 -07:00
mrg
f8146e3f69
Add decoder4x16
2020-10-02 15:52:09 -07:00
mrg
1fc4040607
Add pand4 and pnand4
2020-10-02 14:54:12 -07:00
mrg
d65eb16513
Zjog the WL enable. Min driver is 1.
2020-09-28 12:24:55 -07:00
mrg
6f06bb9dd5
Create sized RBL WL driver in port_address
2020-09-28 11:30:21 -07:00
mrg
c7d32089f3
Create RBL wordline buffer with correct polarity.
2020-09-17 14:45:49 -07:00
Hunter Nichols
73b2277daa
Removed dead code related to older characterization scheme
2020-08-27 17:30:58 -07:00
jcirimel
854d51c721
merge dev
2020-08-19 14:25:41 -07:00
mrg
60224b105f
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2020-08-17 14:20:34 -07:00
jcirimel
e7c9914d77
decoder passing except for bus route
2020-08-13 16:20:39 -07:00
mrg
8dbaa66aa5
Merge branch 'super' into dev
2020-08-12 14:25:13 -07:00
mrg
7ac4574e4f
Use micron units for all simulation in sky130
2020-08-12 13:54:55 -07:00
mrg
5fc6438553
Fix pinv_dec super call
2020-08-12 13:22:28 -07:00
mrg
55814a8f74
Fix syntax errors in pgates for super edits
2020-08-12 11:15:32 -07:00
mrg
30976df48f
Change inheritance inits to use super
2020-08-06 11:33:26 -07:00
mrg
69cab42676
Add pbuf_dec gate
2020-07-27 13:59:55 -07:00
mrg
c7bc01c3a9
Clean up binning. Fix mults to 1 for certain gates.
2020-07-15 17:15:42 -07:00
mrg
e502ee02be
Place before computing height of col mux.
2020-07-13 15:51:46 -07:00
mrg
2b7d89d2c1
Fix netlist_only in sky130
2020-07-13 14:59:31 -07:00
mrg
e49236f8fc
Default drc and lvs errors is skipped.
2020-07-13 14:08:00 -07:00
mrg
c1fedda575
Modifications for min area metal.
...
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
2020-06-30 15:07:34 -07:00
mrg
c10a6a29c0
Simplify precharge pin layer
2020-06-27 08:22:16 -07:00
mrg
ee0a003298
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2020-06-25 08:57:37 -07:00
jcirimel
5941e01b51
add missing parens
2020-06-25 08:02:08 -07:00
jcirimel
59562f2b92
move accuracy_requirement from techfile to config
2020-06-25 06:44:07 -07:00
jcirimel
812cf11e95
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
2020-06-25 06:32:29 -07:00
jcirimel
57b6d49edb
fix pinv size bining
2020-06-25 06:32:07 -07:00
mrg
da900b89ba
Only expand implants in sky130
2020-06-24 13:48:30 -07:00
mrg
ba92467fec
Add no well enclosure for techs without wells
2020-06-24 12:07:47 -07:00
mrg
6c523a7556
use add_enclosure for npc contacts
2020-06-24 11:55:44 -07:00
mrg
e694622f28
use add_enclosure to extend implants
2020-06-24 11:54:59 -07:00
mrg
98ec9442c6
Add npc enclosure for pnand2, pnand3, pnor2
2020-06-24 10:00:00 -07:00
mrg
1340908330
Remove fudge factor for pin spacing
2020-06-24 09:24:26 -07:00
mrg
cddb16dabc
Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
mrg
a32b5b13e8
Rename nwell yoffset for consistency
2020-06-24 08:26:15 -07:00
mrg
e849a9b973
Use different LVS libs based on tech and sky130
2020-06-23 14:53:24 -07:00
mrg
231f90f492
Fix missing space in ptx spice line
2020-06-19 06:47:46 -07:00
mrg
4cb827c3d7
Add redundant implant for s8
2020-06-15 10:08:07 -07:00
mrg
355474ce2c
Playing around with pnand2 pin spacing rules
2020-06-15 10:07:00 -07:00
mrg
6e0008403e
Update new tech name
2020-06-15 10:06:17 -07:00
mrg
7dc33285a7
Add contact to gate design rule to max for spacing inputs
2020-06-14 14:18:08 -07:00
mrg
443c401561
pnand2 B input spaced from top
2020-06-14 14:17:04 -07:00
mrg
91f20f2cf6
Better centering of pinv_dec
2020-06-14 14:09:45 -07:00
mrg
33a32101c9
DRC and LVS fixes for pinv_dec
2020-06-12 15:23:51 -07:00
mrg
jcirimel
Hunter Nichols