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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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5941e01b515b11a8b43168ea84989b4f40a7126a
OpenRAM/compiler/pgates
T
History
jcirimel 5941e01b51 add missing parens
2020-06-25 08:02:08 -07:00
..
pand2.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pand3.py
Vertical gates need both well contacts.
2020-05-13 16:54:35 -07:00
pbuf.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pdriver.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
pgate.py
move accuracy_requirement from techfile to config
2020-06-25 06:44:07 -07:00
pinv_dec.py
move accuracy_requirement from techfile to config
2020-06-25 06:44:07 -07:00
pinv.py
add missing parens
2020-06-25 08:02:08 -07:00
pinvbuf.py
Fix pinvbuf layers
2020-06-09 17:16:35 -07:00
pnand2.py
Add npc enclosure for pnand2, pnand3, pnor2
2020-06-24 10:00:00 -07:00
pnand3.py
Add npc enclosure for pnand2, pnand3, pnor2
2020-06-24 10:00:00 -07:00
pnor2.py
Add npc enclosure for pnand2, pnand3, pnor2
2020-06-24 10:00:00 -07:00
precharge.py
Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
ptristate_inv.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptx.py
Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
pwrite_driver.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
single_level_column_mux.py
Add redundant implant for s8
2020-06-15 10:08:07 -07:00
wordline_driver.py
Change s8 to sky130
2020-06-12 14:23:26 -07:00
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