33 Commits

Author	SHA1	Message	Date
Jesse Cirimelli-Low	c3987f2537	change power ring spacing from magic numbers to drc based	2026-05-07 14:18:58 -07:00
Jesse Cirimelli-Low	e7829cf641	allow tech file to specify connection to power rail per net	2026-05-06 10:42:02 -07:00
Jesse Cirimelli-Low	541d4ff572	parameterize how power ring is connected to crba	2026-05-06 09:50:56 -07:00
Jesse Cirimelli-Low	c7f3ac33cd	sky130 cypress dp working with offset relative to crba	2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low	cb7f117daa	squash commits	2026-04-22 01:33:47 -07:00
Jesse Cirimelli-Low	515591a422	dual port rba lvs clean again with cell library changes	2026-04-14 14:48:26 -07:00
Jesse Cirimelli-Low	b6d98c44d5	singleport cba passing on both tech files	2026-03-17 14:50:43 -07:00
Jesse Cirimelli-Low	53d53ec271	checkpoint from tt submission	2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low	4ce6e0538b	fix col_cap array for dummu compatability ...bitcells next	2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low	f3c1c5fbb2	Merge branch 'singleport_refactor' into array_gen	2025-02-24 23:26:28 -08:00
Eren Dogan	0a1de57cae	Update copyright year	2024-01-03 14:32:44 -08:00
Jesse Cirimelli-Low	066d00f44b	increase power ring crba width for drc	2023-09-01 02:02:41 -07:00
Jesse Cirimelli-Low	0cba6a6050	single port sky130 crba passing lvs	2023-08-30 20:59:02 -07:00
Jesse Cirimelli-Low	8f2e4c6914	power ring working	2023-08-28 22:15:05 -07:00
Jesse Cirimelli-Low	8794070ebc	various refactor changes	2023-08-28 12:31:55 -07:00
Jesse Cirimelli-Low	ba51149dce	placement working for sp capped rba, need fix rowcap patterns	2023-08-26 18:54:07 -07:00
Sam Crow	41344a980b	change array modules to allow rbl=[0, 0]	2023-03-09 10:23:28 -08:00
samuelkcrow	e90964fbda	update copyright	2023-02-21 14:04:31 -08:00
samuelkcrow	51a7161cd7	fix mirroring of cap cells in cap rows	2023-02-14 10:59:00 -08:00
samuelkcrow	2565305158	fix positional getters	2023-02-13 18:45:21 -08:00
samuelkcrow	8d6d8f2f8c	revert variable names to those inherited from bitcell base array	2023-02-13 18:45:21 -08:00
samuelkcrow	c256a5eb44	fix coppied functions from replica array to work correctly in capped array	2023-02-06 19:57:42 -08:00
samuelkcrow	4a22c5c56f	add instance offset to capped array offset getters	2023-02-06 19:40:37 -08:00
samuelkcrow	92a9a1729e	untested update to get_cell_name function used by characterizer	2023-02-06 19:19:02 -08:00
samuelkcrow	3dac89d041	fixing named variables passed between array modules	2023-02-04 21:06:41 -08:00
samuelkcrow	03adf94b6a	fix offsets to match original replica array, and make array translation statically sized	2023-01-26 12:31:14 -08:00
samuelkcrow	ebe163c57e	fix placement bug for cap cells including wrong height from replica array	2023-01-24 11:07:52 -08:00
samuelkcrow	5573c6b241	fix pin shape issue	2023-01-18 22:44:32 -08:00
samuelkcrow	d460eacfcc	standardize rbl arguments interface	2023-01-18 22:43:37 -08:00
samuelkcrow	78c4ba5fc0	clean up comments	2023-01-18 21:01:30 -08:00
samuelkcrow	7021b80506	remove unused side argument from side routing functions	2023-01-18 20:36:36 -08:00
samuelkcrow	8522f32e43	radically simplify unused wordline routing code... bit of a facepalm tbh	2023-01-18 20:32:40 -08:00
samuelkcrow	78cabf9ca3	make capped array name more descriptive and add x mode to tests	2023-01-17 10:20:16 -08:00