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OpenRAM
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3,719 Commits 4 Branches 63 Tags 78 MiB
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3719 Commits

Author SHA1 Message Date
mrg bfb33ecbb4 Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 779d6ad2b2 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg b94dd79125 Add labels to noconn in dummy bitcell for klayout lvs 2021-11-22 11:33:27 -08:00
mrg 735f9cf450 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg 552811b41b Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 43bbd2e722 Fixed incorrect via2 spacing rule in tech file. 2021-11-22 11:33:27 -08:00
mrg 8f296810be Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg 6ee4697711 Change cell names in lvs file 2021-11-22 11:33:27 -08:00
mrg 5d33db0ee4 Add write driver to well connect list 2021-11-22 11:33:27 -08:00
mrg 5dc885a674 Update nwell spacing to be same potential 2021-11-22 11:33:27 -08:00
mrg 2e846cb22f Fix regexes for cells without well taps 2021-11-22 11:33:27 -08:00
mrg acc9b2d223 Connect pwell and bulk when no tap 2021-11-22 11:33:27 -08:00
mrg 141b42dc0e Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg c2e258709b Merge branch 'lvs' into dev 2021-11-22 11:33:12 -08:00
mrg ce40f2ae28 Allow non-unique matching for replica bitcell test. 2021-11-19 09:42:06 -08:00
Jesse Cirimelli-Low 2fb08af684 change col mux array poly routing from straight to 'L' 2021-11-17 17:22:03 -08:00
Bugra Onal c8139cf145 Added OpenPDKS repo to makefile 2021-10-28 18:43:28 +03:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
mrg ccab2f8064 Add CNAME for github pages 2021-10-08 09:11:43 -07:00
Jesse Cirimelli-Low 5792256db1 route spare col 2021-10-05 15:28:20 -07:00
mrg 911f479ecb Modify Makefile to pull from git repo 2021-10-04 16:00:37 -07:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
samuelkcrow dfbf0ba6e1 Make git dependency visible and enforce it. 
resolves #87
 2021-10-04 14:43:14 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
Hunter Nichols 116f102ebf Fixed units in LIB files when cacti is selected as the model. Changed model data gather to only use the extended config. 2021-09-20 16:35:16 -07:00
mrg fe077e79d5 Use local temp DRC/LVS rules file for running. 2021-09-20 11:06:27 -07:00
mrg f2882782e7 Use calibre by default until klayout LVS is clean. 2021-09-20 11:05:49 -07:00
mrg be92282150 Prefer open source over commercial 2021-09-20 11:02:40 -07:00
mrg 10753a0802 Change via2 to 65nm to be compatible with Calibre FreePDK45 deck 2021-09-16 15:42:02 -07:00
mrg 0a91bd01c8 Fix DRC and LVS scripts 2021-09-16 15:37:26 -07:00
mrg 8081bea708 Shrink 70nm contacts to 65nm 2021-09-16 15:28:39 -07:00
Hunter Nichols 11ff8713c5 Added shared config which is imported in all model configs. Shared config only hold model type for now. 2021-09-15 13:00:51 -07:00
mrg c5f372c264 Fix via2 to match incorrect FreePDK45 rules 2021-09-15 11:58:31 -07:00
mrg 11c5a644eb Remove previous breakpoint 2021-09-15 11:43:40 -07:00
mrg f3d1c6edc3 klayout DRC/LVS working 2021-09-15 11:33:39 -07:00
mrg 554b3f4ca7 Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
mrg 8d9a4cc27b PEP8 cleanup 2021-09-07 16:49:44 -07:00
mrg 03f87cd681 Add str function for sram_config 2021-09-07 16:49:31 -07:00
mrg 178f1197ca Use spare rows only for sky130 2021-09-07 16:49:11 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
mrg 83f2d14646 Fix unit test errors. 
Skip test 50s for now.
Change golden power values in xyce delay test.
 2021-09-07 14:07:22 -07:00
mrg b2389fe00f Change tolerance to 30% 2021-09-03 14:04:39 -07:00
mrg 3f031a90db Specify two stage wl_en driver to prevent race condition 2021-09-03 12:52:17 -07:00
Hunter Nichols 6b8d143073 Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter. 2021-09-01 14:27:13 -07:00
mrg 3e9cce0400 Revert github action and disable in repo settings 2021-08-30 09:59:41 -07:00
mrg f42c52509e Change double quote to single 2021-08-30 09:49:22 -07:00