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OpenRAM
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Merge branch 'lvs' into dev

This commit is contained in:
mrg 2021-11-22 11:33:12 -08:00
parent 2fb08af684 ce40f2ae28
commit c2e258709b
1 changed files with 12 additions and 3 deletions
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15
compiler/verify/magic.py
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@ -337,16 +337,25 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False, output_path=
# Netlists match uniquely.
test = re.compile("match uniquely.")
correct = list(filter(test.search, final_results))
uniquely = list(filter(test.search, final_results))
# Netlists match uniquely.
test = re.compile("match correctly.")
correctly = list(filter(test.search, final_results))
# Fail if they don't match. Something went wrong!
if len(correct) == 0:
if len(uniquely) == 0 and len(correctly) == 0:
total_errors += 1
if len(uniquely) == 0 and len(correctly) > 0:
debug.warning("{0}\tLVS matches but not uniquely".format(cell_name))
if total_errors>0:
# Just print out the whole file, it is short.
for e in results:
debug.info(1,e.strip("\n"))
debug.error("{0}\tLVS mismatch (results in {1})".format(cell_name,resultsfile))
debug.error("{0}\tLVS mismatch (results in {1})".format(cell_name,
resultsfile))
else:
debug.info(1, "{0}\tLVS matches".format(cell_name))