luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,256 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

3531 Commits

Author SHA1 Message Date
samuelkcrow 119bcb9197 route unused wordlines (still failing lvs) 2022-12-14 08:12:55 -08:00
mrg 7ddb1a39dc Line wrap output spice subckt and instance lines at 80 characters. 2022-12-12 13:58:30 -08:00
samuelkcrow d224c06b25 placement positions problem fixed, incorrect w,h calculations were the problem 2022-12-10 19:03:55 -08:00
Eren Dogan fe81bbfd7e Fix paths in library usage tests 2022-12-02 20:28:14 -08:00
Eren Dogan 529dbb48c4 Fix sram creation in factory 2022-12-02 20:27:55 -08:00
Eren Dogan 6a4f6cbbed Move sram and sram_config to openram namespace 2022-12-02 15:28:06 -08:00
Eren Dogan fe0826d07c Add unit tests for library usage 2022-12-02 13:04:54 -08:00
Eren Dogan b40a17f4a5 Fix log file for sram_compiler tests 2022-12-02 13:00:12 -08:00
Eren Dogan 7396899769 Add empty build_graph() for dummy bitcells 2022-12-02 12:14:40 -08:00
samuelkcrow 68fb4e3c63 introduced some other bugs but scmos tiling is correct 2022-12-02 09:42:33 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan 175e95dd86 Delete unused scripts 2022-11-30 14:48:51 -08:00
Eren Dogan e15454ebb9 Make sram_config optional for sram 2022-11-29 10:33:32 -08:00
Eren Dogan a37d41b406 Fix typo 2022-11-27 16:41:28 -08:00
Eren Dogan 316f75861b Fix unit tests running on docker with a hack for now 2022-11-27 14:32:55 -08:00
Eren Dogan 2e7206343e Remove unnecessary imports 2022-11-27 13:11:10 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
samuelkcrow ac8a15acc0 fix get_replica_top and get_replica_left return values 2022-11-21 17:42:50 -08:00
Eren Dogan e718106d87 Change is_unit_test to False by default 2022-11-21 14:52:57 -08:00
Eren Dogan e821b4a75e Print info regarding which directories are being used 2022-11-10 22:24:41 -08:00
Eren Dogan f95ff3c694 Fix library path in globals.setup_paths() 2022-11-10 21:50:31 -08:00
Eren Dogan 845f32805f Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
Eren Dogan 62700e4d2b Fix OPENRAM_HOME path for library 2022-11-04 15:47:38 -07:00
Eren Dogan 557b2e7459 Reorganize library files to include everything 2022-11-04 15:10:44 -07:00
Eren Dogan 740cff985a Inform user when library's tech is used 2022-11-03 22:02:05 -07:00
mrg a213d3b0f6 Merge branch 'dev' into library 2022-11-02 16:20:56 -07:00
mrg b1a88d8c8a Remove variable reference in ifdef 2022-11-02 08:02:22 -07:00
Eren Dogan dacc0acd4d Fix paths while initializing 2022-10-25 13:01:02 -07:00
Eren Dogan 92460d2080 Move the compiler script to the root 2022-10-25 12:22:57 -07:00
Eren Dogan dc9d1e00d8 Add setup files for package 2022-10-25 12:22:18 -07:00
samuelkcrow 5a82c45a33 Change how lists of BLs and WLs are named and organized for proper connection between these modules 2022-10-24 20:08:13 -07:00
mrg 9b6eb4a120 Fix whitespace 2022-10-20 16:38:23 -07:00
mrg 8fd08916a1 Move is_non_inverting graph code to bitcell_base class to work with pbitcell too. 2022-10-20 15:16:10 -07:00
mrg aeca2c6b88 Allow any definition of KEEP to keep temp files 2022-10-20 14:31:26 -07:00
samuelkcrow 55d89fbae8 copy supply pins to top level in replica array, now passing tests 2022-10-19 17:13:54 -07:00
samuelkcrow f9419e8ff7 fix self.rbls and fix handling of rbl WLs (kinda) 2022-10-17 20:51:42 -07:00
samuelkcrow a1ca7c312d remove grounded WLs from replica array 2022-10-11 11:43:26 -07:00
samuelkcrow cfd52a6065 fix offsets so array ends up at 0,0 2022-09-26 14:24:16 -07:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
samuelkcrow 37dee02161 Merge branch 'dev' into no_rbl 2022-09-13 12:34:57 -07:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
samuelkcrow 004ee3748d add option to keep tmp files when running tests with make 2022-09-08 13:40:48 -07:00
samuelkcrow f1f18b3b54 replica code working but failing lvs 2022-09-07 19:32:25 -07:00
samuelkcrow 3ef52789be first pass splitting replica array into capped and replica array modules 2022-09-07 12:39:35 -07:00
samuelkcrow fe0cfac6c8 tests for new capped array module 2022-09-07 12:39:01 -07:00
Bugra Onal 57d7a78421 Merge branch 'multibank' into dev 2022-08-30 09:19:19 -07:00
Bugra Onal 1a214a7309 Fixed utest 25 golden 2022-08-30 09:17:51 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
Bugra Onal c0c15537d9 Added golden files for freepdk test 25 2022-08-18 11:04:53 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal a7c6406d0d Changed verilog file naming convention 2022-08-18 10:36:54 -07:00
Bugra Onal 1a23d156c0 remove references to bank_sel 2022-08-18 10:33:46 -07:00
Bugra Onal 242d90f543 Code format fixes 2022-08-13 13:58:53 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal b33c2ab96c Fixed test 25 golden files 2022-08-12 21:33:40 -07:00
Bugra Onal 6ba2a9bca7 Make sure num_wmasks is 0 when no wmask is generated 2022-08-10 16:35:39 -07:00
Bugra Onal f743b1f068 Convert to new modules format 2022-08-10 16:34:49 -07:00
Bugra Onal 623c1ac02f Convert unit test 25 to new modules convert 2022-08-10 16:33:50 -07:00
Bugra Onal dc1626879e Characterizer wmask check for write_size 2022-08-10 16:11:19 -07:00
Bugra Onal 2d849aef39 Write size updated in recompute_sizes 2022-08-10 15:36:41 -07:00
Bugra Onal 48fce6485d write_size None initialization fixed 2022-08-04 16:37:21 -07:00
Bugra Onal 2ed107f9ff Fix the total addr_size 2022-08-04 16:36:26 -07:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
samuelkcrow 1177df6193 move most of place_instances to base 2022-08-01 10:33:48 -07:00
Bugra Onal 7fe0f647ef fix 2022-07-28 17:00:16 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 6efe974d7b Delete sram_base form rebase 2022-07-28 16:02:39 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
Bugra Onal 02d8eca640 Fix indentation 2022-07-28 15:07:19 -07:00
Bugra Onal 36e23dc80f Moved template module to new modules folder 2022-07-28 15:05:34 -07:00
Bugra Onal bac40fa630 Removed SRAM directory 2022-07-28 15:04:53 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal d36f74a514 Not mathcing whitespace bug fixed 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal 9bd3f1b45a None check syntax fix 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal e130ba736c Fixed indent error on write_size init 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bbcbddd934 Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 2b1d0bd9f7 Template module done 2022-07-28 15:03:41 -07:00
Bugra Onal 0970095415 Bank select 2022-07-28 15:03:41 -07:00
Bugra Onal 859548f19f Templatable verilog file 2022-07-28 15:03:41 -07:00
Bugra Onal f08da6acc5 Fixed globals conflict 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal a0c6a0ad03 Set write_size default to word_size 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00