 mrg
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92fc30005c
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Use factory in and_dec tests
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2020-06-22 16:55:49 -07:00 |
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mrg
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40edbfa51f
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Error out on single port in sky130
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2020-06-22 15:41:59 -07:00 |
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mrg
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cd23b31ab4
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-06-22 12:55:45 -07:00 |
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mrg
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0926eab9f5
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PEP8 formatting
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2020-06-22 12:55:18 -07:00 |
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mrg
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54120f8405
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Add option for removing subckt/instances of cells for row/col caps
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2020-06-22 12:35:37 -07:00 |
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mrg
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a13d535945
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PEP8 cleanup
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2020-06-22 11:33:02 -07:00 |
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 Joey Kunzler
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8166adc512
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Merge branch 'dev' into s8_update
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2020-06-19 15:35:49 -07:00 |
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Joey Kunzler
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208c652653
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added error for sky130 with invalid x mirroring (for lvs)
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2020-06-19 13:59:33 -07:00 |
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mrg
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a2d160dbf5
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Copy magic config for filter code
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2020-06-19 13:40:45 -07:00 |
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mrg
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5872f553e1
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Rename tests for consistency
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2020-06-19 08:53:35 -07:00 |
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mrg
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239b3ea007
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Make wmask test a 1rw/1r
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2020-06-19 08:49:48 -07:00 |
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mrg
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617a84d4b8
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Fix output name of magic gds filter
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2020-06-19 07:15:27 -07:00 |
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mrg
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94c480911b
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ngspice raw save doesn't work with measures
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2020-06-19 07:09:15 -07:00 |
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mrg
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231f90f492
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Fix missing space in ptx spice line
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2020-06-19 06:47:46 -07:00 |
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mrg
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403ea17039
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PEP8 formatting
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2020-06-18 14:55:01 -07:00 |
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mrg
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69f5621245
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Save raw file from ngspice
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2020-06-18 14:54:36 -07:00 |
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mrg
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7dfc462ef6
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Add magic filter before calibre for sky130
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2020-06-15 13:58:26 -07:00 |
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mrg
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abb5ff7bae
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Separate route conditions for s8
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2020-06-15 10:30:27 -07:00 |
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mrg
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e331d6fae8
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Permute bus order to avoid conflict in control_logic
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2020-06-15 10:25:53 -07:00 |
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mrg
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a862cf3cb2
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Test more single level col mux configs
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2020-06-15 10:17:54 -07:00 |
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mrg
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4cb827c3d7
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Add redundant implant for s8
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2020-06-15 10:08:07 -07:00 |
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mrg
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355474ce2c
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Playing around with pnand2 pin spacing rules
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2020-06-15 10:07:00 -07:00 |
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mrg
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6e0008403e
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Update new tech name
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2020-06-15 10:06:17 -07:00 |
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mrg
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79b3b9a8b0
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Switch input/output layers for predecodes
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2020-06-15 10:06:04 -07:00 |
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mrg
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6c04166876
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Update port data wmask tests
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2020-06-15 06:05:05 -07:00 |
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mrg
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02352c35d7
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Fix hard coded layer in wmask
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2020-06-14 17:10:32 -07:00 |
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mrg
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52ee7b0a19
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Disable perimeter pins and make an option
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2020-06-14 16:44:10 -07:00 |
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mrg
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78be9f367a
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Add brain-dead router pins to perimeter
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2020-06-14 15:52:09 -07:00 |
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mrg
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9930b5f3f6
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Do not run tapless unit tests
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2020-06-14 14:18:25 -07:00 |
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mrg
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7dc33285a7
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Add contact to gate design rule to max for spacing inputs
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2020-06-14 14:18:08 -07:00 |
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mrg
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8e8a97cc4b
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Add correct boundary to SRAM
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2020-06-14 14:17:35 -07:00 |
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mrg
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443c401561
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pnand2 B input spaced from top
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2020-06-14 14:17:04 -07:00 |
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mrg
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91f20f2cf6
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Better centering of pinv_dec
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2020-06-14 14:09:45 -07:00 |
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mrg
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8f1dc7eeea
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Include mirror/rotate on translate_all boundary update
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2020-06-13 06:50:53 -07:00 |
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mrg
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33a32101c9
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DRC and LVS fixes for pinv_dec
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2020-06-12 15:23:51 -07:00 |
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mrg
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443b8fbe23
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Change s8 to sky130
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2020-06-12 14:23:26 -07:00 |
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mrg
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54e4d147f6
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Rail to ptx spacing based on routing layer not m1
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2020-06-11 15:03:50 -07:00 |
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mrg
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e9780ea599
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Add non-preferred directions for channel routes
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2020-06-11 15:03:36 -07:00 |
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mrg
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8d52794c32
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Remove printf in precharge
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2020-06-11 11:57:52 -07:00 |
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mrg
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7ad2d54a69
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Add pin and label purposes
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2020-06-11 11:54:51 -07:00 |
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mrg
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1a2e0046b1
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Add contact to gate spacing for precharge
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2020-06-11 11:54:34 -07:00 |
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mrg
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089331ced3
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Add stdc bounding box too
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2020-06-11 11:54:16 -07:00 |
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mrg
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098219d56c
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Add npc enclosure to poly contacts
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2020-06-11 11:53:59 -07:00 |
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mrg
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f973dd6a5c
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Save LVS model with no u too for Calibre
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2020-06-11 11:53:34 -07:00 |
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mrg
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dff28a9997
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Merge branch 'tech_migration' into dev
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2020-06-10 17:09:05 -07:00 |
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mrg
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196e5998c8
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Half poly space per cell at top and bottom.
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2020-06-10 16:52:51 -07:00 |
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mrg
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fdf92d0da1
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Rename test 14
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2020-06-10 16:41:26 -07:00 |
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mrg
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0b4b5e7133
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More exact input spacing in pnand3
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2020-06-10 16:19:24 -07:00 |
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mrg
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bfd1abc79f
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Replica column pins start at 0 height.
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2020-06-10 14:58:55 -07:00 |
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mrg
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469cd260b9
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Change bitcell array name to match
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2020-06-10 14:54:20 -07:00 |
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