mrg
37fcf3bf37
Move classes to individual file.
2019-07-16 15:18:04 -07:00
mrg
8ca656959b
Change direction of RBL bitline pins
2019-07-16 15:09:46 -07:00
mrg
b546ecce2c
Check 2 ports only for layout.
2019-07-16 14:11:54 -07:00
mrg
12fa36317e
Cleanup unit test. Fix s_en control bug for r-only.
2019-07-16 13:51:31 -07:00
mrg
2f55911604
Simplify column decoder placement.
2019-07-16 11:55:25 -07:00
mrg
70ee026fcf
Add cell names to psingle_bank test
2019-07-16 11:54:57 -07:00
mrg
42ad0cd282
Add pbitcell RW test
2019-07-16 11:54:39 -07:00
mrg
bea07c2319
SRAM with RBL integration in array.
2019-07-16 09:04:58 -07:00
mrg
37c15937e2
Add multiple control logic port types.
2019-07-15 17:07:50 -07:00
mrg
e550d6ff10
Port name maps between bank and replica array working.
2019-07-15 11:29:29 -07:00
mrg
2271946eef
Fix replica array pin names
2019-07-12 14:39:56 -07:00
mrg
8815ddf7f1
Remove unnecessary feasible period search.
2019-07-12 11:55:42 -07:00
mrg
9092fa4ee6
Remove multiport control logic test since it doesn't have a bitcell anymore.
2019-07-12 11:18:47 -07:00
mrg
d72691f6c2
Make mirror optional argument
2019-07-12 11:14:47 -07:00
mrg
a189b325ed
Merge remote-tracking branch 'origin/dev' into rbl_revamp
2019-07-12 11:10:07 -07:00
mrg
80145c0a92
Only enable pdb post-mortem when not purging temp for debug.
2019-07-12 10:57:59 -07:00
mrg
17d144b5b5
Clean up multiport test options to be consistent.
2019-07-12 10:39:55 -07:00
mrg
aa552f8e96
Remove debug trace
2019-07-12 10:17:33 -07:00
mrg
043018e8ba
Functional tests working with new RBL.
2019-07-12 08:42:36 -07:00
mrg
0b13225913
Single banks working with new RBL
2019-07-11 14:47:27 -07:00
mrg
b841fd7ce3
Replica bitcell array with arbitrary RBLs working
2019-07-10 15:56:51 -07:00
Bin Wu
c9c839ca46
fix the delay measure bug in pex tests
2019-07-10 04:39:40 -07:00
Bin Wu
e4070ddad8
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2
2019-07-10 03:09:12 -07:00
jsowash
5258016c9f
Changed location of port for din_reg.
2019-07-06 12:27:24 -07:00
jsowash
6fe78fe04a
Removed begin end for Verilog without wmask.
2019-07-06 11:29:34 -07:00
jsowash
24bfaa3b76
Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
2019-07-05 15:55:03 -07:00
jsowash
ad9193ad5a
Verified 1rw mask writing and changed verilog.py accordingly.
2019-07-05 15:08:59 -07:00
mrg
9dab0be737
Single bank working with replica array.
2019-07-05 13:44:29 -07:00
mrg
b9d993c88b
Add dummy bitcell module.
...
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
2019-07-05 12:58:52 -07:00
jsowash
f29631695c
Finished merge
2019-07-05 11:43:31 -07:00
jsowash
150259e2ba
Added write_size to control_logic_r parameters.
2019-07-05 11:40:02 -07:00
mrg
f542613d78
Correct wordline_driver enable to en, not en_bar.
2019-07-05 10:31:05 -07:00
mrg
bfe4213fce
Port address added to entire SRAM.
2019-07-05 09:44:42 -07:00
mrg
4c6556f1bc
Add port address module
2019-07-05 09:04:48 -07:00
mrg
c0f9cdbc12
Create port address module
2019-07-05 09:03:52 -07:00
mrg
dd62269e0b
Some cleanup
2019-07-05 08:18:58 -07:00
jsowash
02a0cd71ac
fixed merge conflict
2019-07-04 11:14:32 -07:00
jsowash
125112b562
Added wmask flip flop. Need work on placement still.
2019-07-04 10:34:14 -07:00
mrg
3176ae9d50
Fix pnand2 height in bank select. Unsure how it passed before.
2019-07-03 15:12:22 -07:00
Matt Guthaus
f914ab0ece
Re-enable replica tests
2019-07-03 14:57:47 -07:00
Matt Guthaus
0cb86b8ba2
Exclude new precharge in graph build
2019-07-03 14:46:20 -07:00
mrg
8b0b2e2817
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
mrg
70c83f20b6
Fixes to pass unit tests.
...
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
2019-07-03 13:37:56 -07:00
mrg
bc4a3ee2b7
New port_data module works in SCMOS
2019-07-03 13:17:12 -07:00
jsowash
474ac67af5
Added optional write_size and wmask.
2019-07-03 10:14:15 -07:00
mrg
244604fb0d
Data port module working by itself.
2019-07-02 15:35:53 -07:00
mrg
2abe859df1
Fix shared bank offset.
2019-07-01 16:29:59 -07:00
jsowash
67c6cdf3bb
Fixed error where word_size was compared to num_words and added write_size to control_logic.py
2019-07-01 15:51:40 -07:00
Bin Wu
9ce968b446
megre with dev changes
2019-06-30 00:50:18 -07:00
Bin Wu
1fcb20f846
clean pex test based on feedback
2019-06-30 00:16:04 -07:00
mrg
Bin Wu
jsowash