luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
OpenRAM/compiler
History
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 		2019-07-05 12:58:52 -07:00
..
base Create port address module 2019-07-05 09:03:52 -07:00
bitcells Add dummy bitcell module. 2019-07-05 12:58:52 -07:00
characterizer Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
datasheet Fix space before comment 2019-06-14 08:43:41 -07:00
drc Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
example_configs Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
gdsMill Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
modules Add dummy bitcell module. 2019-07-05 12:58:52 -07:00
pgates Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
router Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
sram Add dummy bitcell module. 2019-07-05 12:58:52 -07:00
tests Add dummy bitcell module. 2019-07-05 12:58:52 -07:00
verify Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Some cleanup 2019-07-05 08:18:58 -07:00
gen_stimulus.py Fix space before comment 2019-06-14 08:43:41 -07:00
globals.py Add dummy bitcell module. 2019-07-05 12:58:52 -07:00
openram.py Fix space before comment 2019-06-14 08:43:41 -07:00
options.py Add dummy bitcell module. 2019-07-05 12:58:52 -07:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
view_profile.py Fix space before comment 2019-06-14 08:43:41 -07:00