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Changed location of port for din_reg.

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jsowash
2019-07-06 12:27:24 -07:00
parent 6fe78fe04a
commit 5258016c9f
1 changed files with 1 additions and 1 deletions
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compiler/base/verilog.py
+1 -1
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@@ -197,7 +197,7 @@ class verilog:
self.vf.write(" mem[ADDR{0}_reg][{1}:{2}] = DIN{0}_reg[{1}:{2}];\n".format(port,upper,lower))
self.vf.write(" end\n")
else:
self.vf.write(" mem[ADDR{0}_reg] = DIN_reg{0};\n".format(port))
self.vf.write(" mem[ADDR{0}_reg] = DIN{0}_reg;\n".format(port))
self.vf.write(" end\n")
def add_read_block(self, port):