mrg 0b13225913 Single banks working with new RBL

2019-07-11 14:47:27 -07:00

..

base

Create port address module

2019-07-05 09:03:52 -07:00

bitcells

Single banks working with new RBL

2019-07-11 14:47:27 -07:00

characterizer

Undid change to add bitcell as input to array mod.

2019-06-25 18:26:13 -07:00

datasheet

Fix space before comment

2019-06-14 08:43:41 -07:00

drc

Merge branch 'pep8_cleanup' into dev

2019-06-14 08:47:10 -07:00

example_configs

Add giant example for front-end mode

2019-04-01 15:49:01 -07:00

gdsMill

Added functionality to express polygons in LEF files.

2019-06-25 09:20:00 -07:00

modules

Single banks working with new RBL

2019-07-11 14:47:27 -07:00

pgates

Merge branch 'dev' into rbl_revamp

2019-07-03 14:05:28 -07:00

router

Merge branch 'pep8_cleanup' into dev

2019-06-14 08:47:10 -07:00

sram

Replica bitcell array with arbitrary RBLs working

2019-07-10 15:56:51 -07:00

tests

Single banks working with new RBL

2019-07-11 14:47:27 -07:00

verify

Merge branch 'pep8_cleanup' into dev

2019-06-14 08:47:10 -07:00

debug.py

Some cleanup

2019-07-05 08:18:58 -07:00

gen_stimulus.py

Fix space before comment

2019-06-14 08:43:41 -07:00

globals.py

Add dummy bitcell module.

2019-07-05 12:58:52 -07:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Fix space before comment

2019-06-14 08:43:41 -07:00

options.py

Add dummy bitcell module.

2019-07-05 12:58:52 -07:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Merged and fixed conflicts with dev

2019-06-25 16:55:50 -07:00

view_profile.py

Fix space before comment

2019-06-14 08:43:41 -07:00