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OpenRAM
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2,445 Commits 4 Branches 63 Tags 78 MiB
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562 Commits

Author SHA1 Message Date
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00
mrg f1c1adc9bd Simplify supply contacts in delay chain. 2020-04-21 16:12:54 -07:00
mrg 0f6998a1c5 PEP8 cleanup 2020-04-21 15:36:38 -07:00
mrg cd66ddb37c Add supply rails to dff array. PEP8 cleanup. 2020-04-21 15:21:29 -07:00
mrg f6135f3471 PEP8 formatting 2020-04-20 16:38:30 -07:00
mrg 7995451cbb PEP8 formatting 2020-04-20 14:45:18 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
mrg 843e9414df Parameterize vdd and gnd pin in write driver array. 2020-04-16 11:28:35 -07:00
mrg 770533e7b1 Parameterize vdd and gnd pin in sense amp array. 2020-04-16 11:27:26 -07:00
mrg 9d2902de9e Conditional well spacing 2020-04-15 15:55:49 -07:00
mrg e95c97d7a5 PEP8 cleanup 2020-04-15 14:29:43 -07:00
mrg 331a4f4606 Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
mrg 0941ebc3da Fix well spacing issue 2020-04-14 14:08:07 -07:00
mrg 32d190b8b1 Jog connection on M1 for bank select. 2020-04-14 12:15:56 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
mrg 7888e54fc4 Remove dynamic bitcell multiple detection. 
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
 2020-04-09 11:38:18 -07:00
mrg 8a55c223df Use single height for netlist_only mode 2020-04-09 09:48:54 -07:00
mrg 58fbc5351a Change rows to outputs in hierarchical decoder 2020-04-08 17:05:16 -07:00
mrg 0c27942bb2 Dynamically try and DRC decoder for height 2020-04-08 16:45:28 -07:00
Jesse Cirimelli-Low b59c789dec remove whitespace 2020-04-05 03:58:26 -07:00
Jesse Cirimelli-Low 8b33cb519f Merge branch 'dev' into custom_mod 2020-04-03 17:05:56 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 5349323acd PEP8 cleanup. DRC/LVS returns errors. 2020-04-02 09:47:39 -07:00
mrg a9d3548be1 Refactor drc/lvs error output 2020-04-01 15:54:06 -07:00
Jesse Cirimelli-Low cdf0315a90 Merge branch 'dev' into custom_mod 2020-04-01 15:35:33 -07:00
mrg 7956b63d9f Add licon option to precharge 2020-04-01 11:26:45 -07:00
mrg d916322b74 PEP8 updates 2020-03-31 10:15:46 -07:00
Joey Kunzler b0d2946c80 update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
Jesse Cirimelli-Low 341bde7a48 Merge branch 'dev' into custom_mod 2020-03-26 02:40:37 -07:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 1a2efd77ad Move rbl route away from bitcell array 2020-03-06 09:48:20 -08:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg ad98137cd4 Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
mrg 9c1f0657dd PEP8 Formatting 2020-03-05 11:58:36 -08:00
mrg 7adeef6c9e PEP8 Formatting 2020-03-05 10:21:18 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
Joey Kunzler d7529ce526 Vdd/gnd via stacks now use perferred directions, added cell property to override 2020-03-04 17:05:19 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
Jesse Cirimelli-Low f62016ad9f revert dff_buf for no body contact 2020-03-03 12:40:08 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
Bastian Koppelmann 0e641bf905 Remove write_driver_array.py.orig 
this was the remainder of applying a diff using "patch". To avoid this
mistake, add the filetypes created by "patch" to the .gitignore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-21 13:29:43 +01:00
Matt Guthaus da4c69ab98 Merge branch 'pin-pull3' into dev 2020-02-20 09:07:58 -08:00
Hunter Nichols c1cb6bf512 Changed layout input names of s_en AND gate to match the schematic 2020-02-19 23:32:11 -08:00
Hunter Nichols 843fce41d7 Fixed issues with sen control logic for read ports. 2020-02-19 03:06:11 -08:00
Bastian Koppelmann 76256a2f1b sense_amp: Allow custom pin names 
we don't want to propagate the sense amp's bl/br names out of the
sense_amp_array. Thus the sense_amp_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:12 +01:00
Bastian Koppelmann 680dc6d2c7 sense_amp/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:06 +01:00
Bastian Koppelmann 9a12b68680 write_driver: Allow custom pin names 
we don't want to propagate the write driver bl/br names out of the
write_driver_array. Thus the write_driver_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:25:00 +01:00
Bastian Koppelmann c06cb2bfc2 write_driver/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:23:26 +01:00