 mrg
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2c76a2680f
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Adjust openram options.
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
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2020-11-05 13:12:26 -08:00 |
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mrg
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fb0b285652
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-04 10:40:20 -08:00 |
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mrg
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6e12d4d46c
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Skip tri gate array test
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2020-11-04 06:57:51 -08:00 |
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mrg
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29ac541b28
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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mrg
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87419bd640
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Fix bitcell and pbitcell with different cell names
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2020-11-03 11:30:40 -08:00 |
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mrg
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cb3e9517bb
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Use cell_properties to override cell names
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2020-11-03 07:06:01 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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8c4584daa1
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Missing import fix.
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2020-11-03 06:09:42 -08:00 |
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mrg
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f9787eb878
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Use bitcell_base for all bitcells. Fix missing setup_bitcell call
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2020-11-02 17:00:15 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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mrg
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cbf9c48504
|
Names in skiptests changed. Reduce grid router verbosity.
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2020-10-23 09:22:59 -07:00 |
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mrg
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43d2058b3c
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Remove temp files
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2020-10-08 10:35:27 -07:00 |
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mrg
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9a0fc8047b
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Remove diff
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2020-10-08 09:53:52 -07:00 |
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mrg
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7076c376e0
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Remove log from branch
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2020-10-08 09:53:17 -07:00 |
|
 jcirimel
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1e7ae06b7e
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fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
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2020-10-08 05:32:03 -07:00 |
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jcirimel
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d40c3588ed
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no wl for col end
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2020-10-08 03:34:16 -07:00 |
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jcirimel
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4a1a7e637e
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merge in dev
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2020-10-07 11:54:07 -07:00 |
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jcirimel
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888646cdf9
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merge in wlbuf and begin work on 32kb memory
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2020-10-06 05:03:59 -07:00 |
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mrg
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a145a37cf7
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PEP8 fixes in regress.py
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2020-10-05 15:56:12 -07:00 |
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mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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mrg
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c4952ca8be
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Skip full sram pex test too slow
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2020-10-05 13:51:20 -07:00 |
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mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
|
Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
|
64cc620440
|
Add sram pex test
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2020-10-02 14:55:10 -07:00 |
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mrg
|
1fc4040607
|
Add pand4 and pnand4
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2020-10-02 14:54:12 -07:00 |
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mrg
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a62b82128c
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Skip riscv func test because too slow
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2020-10-02 13:33:58 -07:00 |
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mrg
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1e24b780bb
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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mrg
|
b32c123dab
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PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
|
2020-10-01 11:10:18 -07:00 |
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|
Matt Guthaus
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112d57d90a
|
Enable riscv tests
|
2020-09-30 12:39:40 -07:00 |
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mrg
|
f4e6a8895b
|
Update riscv unit test
|
2020-09-30 08:50:58 -07:00 |
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|
jcirimel
|
7cbf456a4f
|
sky130 rba done
|
2020-09-30 07:34:05 -07:00 |
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|
mrg
|
b147e8485c
|
PEP8 formatting
|
2020-09-29 16:52:27 -07:00 |
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|
mrg
|
8e908f016e
|
PEP8 formatting
|
2020-09-29 13:43:59 -07:00 |
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|
mrg
|
54890a8d77
|
Add new golden data
|
2020-09-29 13:43:34 -07:00 |
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|
mrg
|
0c280e062a
|
Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.
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2020-09-29 11:35:58 -07:00 |
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mrg
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9032bb9869
|
Add global wordline delay test
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2020-09-29 10:28:57 -07:00 |
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|
mrg
|
1eb8798bb6
|
Add global functional test
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2020-09-28 16:12:09 -07:00 |
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|
mrg
|
6f06bb9dd5
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
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|
jcirimel
|
3dd72cdeac
|
progress with rba pin mismatch
|
2020-09-23 08:37:32 -07:00 |
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|
jcirimel
|
17e6e5eb16
|
row end col done
|
2020-09-23 08:02:56 -07:00 |
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|
jcirimel
|
5c263e0001
|
rep col done w/o power pins
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2020-09-23 06:24:52 -07:00 |
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|
jcirimel
|
7afe3ea52c
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replica col arrangement done
|
2020-09-23 04:51:09 -07:00 |
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|
jcirimel
|
efdc171b14
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make split wl specific to each port
|
2020-09-23 00:08:34 -07:00 |
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|
mrg
|
392afd4d4b
|
Add unit test for hierarchical wordline.
|
2020-09-15 13:46:21 -07:00 |
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|
jcirimel
|
d22164bd48
|
single port progess
|
2020-09-14 18:11:38 -07:00 |
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|
mrg
|
55dd4d0c47
|
Global bitcell array working
|
2020-09-14 14:35:52 -07:00 |
|
|
mrg
|
12fd60e8c3
|
Fix pbitcell array test
|
2020-09-09 12:02:09 -07:00 |
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|
mrg
|
7bb21fb73f
|
Updates to local and global arrays to make bitline and wordlines consistent.
|
2020-09-09 11:54:46 -07:00 |
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|
jcirimel
|
73443c8c95
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Merge branch 'dev' into s8_single_port
|
2020-09-01 15:37:10 -07:00 |
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