luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
5c263e0001caf6311477030ab91e0ea877e12728
OpenRAM/compiler/tests
T
History
jcirimel 5c263e0001 rep col done w/o power pins
2020-09-23 06:24:52 -07:00
..
configs
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
golden
Update golden results with new lib syntax
2020-04-22 10:40:04 -07:00
00_code_format_check_test.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
01_library_drc_test.py
Fix ignore gds files
2019-12-16 15:39:32 -08:00
02_library_lvs_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
03_contact_test.py
Add nwell/pwell tap test
2020-02-03 18:41:06 +00:00
03_path_test.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
03_ptx_1finger_nmos_test.py
Add source drain contact options to ptx.
2020-03-23 11:36:45 -07:00
03_ptx_1finger_pmos_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
03_ptx_3finger_nmos_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
03_ptx_3finger_pmos_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
03_ptx_4finger_nmos_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
03_ptx_4finger_pmos_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
03_ptx_no_contacts_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
03_wire_test.py
Cleanup.
2019-12-17 23:07:01 +00:00
04_and2_dec_test.py
Use factory in and_dec tests
2020-06-22 16:55:49 -07:00
04_and3_dec_test.py
Use factory in and_dec tests
2020-06-22 16:55:49 -07:00
04_and4_dec_test.py
Skip and4_dec test
2020-06-23 10:08:28 -07:00
04_dff_buf_test.py
Rename dff_buf test
2020-06-09 17:18:19 -07:00
04_dummy_pbitcell_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_pand2_test.py
Remove vertical pand gates
2020-06-09 16:40:59 -07:00
04_pand3_test.py
Remove vertical pand gates
2020-06-09 16:40:59 -07:00
04_pbitcell_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_pbuf_dec_8x_test.py
Add pbuf_dec gate
2020-07-27 13:59:55 -07:00
04_pbuf_test.py
Fix pbuf test info
2020-07-27 13:59:35 -07:00
04_pdriver_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
04_pinv_1x_beta_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_pinv_1x_test.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
04_pinv_2x_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_pinv_10x_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_pinv_100x_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
04_pinv_dec_1x_test.py
DRC and LVS fixes for pinv_dec
2020-06-12 15:23:51 -07:00
04_pinvbuf_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_pnand2_test.py
Do not run tapless unit tests
2020-06-14 14:18:25 -07:00
04_pnand3_test.py
Do not run tapless unit tests
2020-06-14 14:18:25 -07:00
04_pnor2_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
04_precharge_1rw_1r_test.py
Fix precharge offset. Move well rules to design class.
2020-06-09 15:28:50 -07:00
04_precharge_pbitcell_test.py
updated pbitcell test names
2020-04-21 17:20:29 -07:00
04_precharge_test.py
Separate pbitcell tests for precharge
2020-04-01 11:14:50 -07:00
04_pwrite_driver_test.py
Fix permissions on pwrite_driver test
2019-11-20 11:49:39 -08:00
04_replica_pbitcell_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
04_single_level_column_mux_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
04_single_level_column_mux_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
04_single_level_column_mux_test.py
Add col mux tests for multiport
2020-06-03 10:01:02 -07:00
04_wordline_driver_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
05_bitcell_array_1rw_1r_test.py
Change bitcell array name to match
2020-06-10 14:54:20 -07:00
05_bitcell_array_test.py
single port progess
2020-09-14 18:11:38 -07:00
05_dummy_array_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
05_pbitcell_array_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
06_hierarchical_decoder_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
06_hierarchical_decoder_pbitcell_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
06_hierarchical_decoder_test.py
decoder passing except for bus route
2020-08-13 16:20:39 -07:00
06_hierarchical_predecode2x4_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
06_hierarchical_predecode2x4_pbitcell_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
06_hierarchical_predecode2x4_test.py
Add 1rw_1r tests
2020-06-03 14:30:15 -07:00
06_hierarchical_predecode3x8_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
06_hierarchical_predecode3x8_pbitcell_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
06_hierarchical_predecode3x8_test.py
Add 1rw_1r tests
2020-06-03 14:30:15 -07:00
06_hierarchical_predecode4x16_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
07_single_level_column_mux_array_1rw_1r_test.py
Test more single level col mux configs
2020-06-15 10:17:54 -07:00
07_single_level_column_mux_array_pbitcell_test.py
Update mirroring in port_data for bitcell mirrored arrays
2020-06-05 11:29:31 -07:00
07_single_level_column_mux_array_test.py
Test more single level col mux configs
2020-06-15 10:17:54 -07:00
08_precharge_array_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
08_precharge_array_test.py
Update mirroring in port_data for bitcell mirrored arrays
2020-06-05 11:29:31 -07:00
08_wordline_buffer_array_test.py
Draft local and global arrays. Ensure rows before cols in usage.
2020-07-23 14:43:14 -07:00
08_wordline_driver_array_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
08_wordline_driver_array_pbitcell_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
08_wordline_driver_array_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
09_sense_amp_array_1rw_1r_test.py
Add more s8 skip tests
2020-06-10 10:14:52 -07:00
09_sense_amp_array_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
09_sense_amp_array_test_pbitcell.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
09_sense_amp_array_test.py
Update mirroring in port_data for bitcell mirrored arrays
2020-06-05 11:29:31 -07:00
10_write_driver_array_1rw_1r_test.py
Add u+x permissions to new tests
2020-06-24 08:19:25 -07:00
10_write_driver_array_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
10_write_driver_array_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
10_write_driver_array_test.py
split pbitcell tests
2020-04-17 12:26:18 -07:00
10_write_driver_array_wmask_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
10_write_driver_array_wmask_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
10_write_driver_array_wmask_test.py
split pbitcell tests
2020-04-17 12:26:18 -07:00
10_write_mask_and_array_1rw_1r_test.py
Add u+x permissions to new tests
2020-06-24 08:19:25 -07:00
10_write_mask_and_array_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
10_write_mask_and_array_test.py
split pbitcell tests
2020-04-17 12:26:18 -07:00
11_dff_array_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
11_dff_buf_array_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
12_tri_gate_array_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
13_delay_chain_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
14_replica_bitcell_array_1rw_1r_test.py
Fix replica bitcell array for right only RBL
2020-08-18 15:47:52 -07:00
14_replica_bitcell_array_test.py
Update interface of RBL array
2020-08-17 17:19:07 -07:00
14_replica_column_1rw_1r_test.py
Update interface of RBL array
2020-08-17 17:19:07 -07:00
14_replica_column_test.py
Update interface of RBL array
2020-08-17 17:19:07 -07:00
14_replica_pbitcell_array_test.py
Update interface of RBL array
2020-08-17 17:19:07 -07:00
15_global_bitcell_array_test.py
Still working on array refactor
2020-08-25 11:50:44 -07:00
15_local_bitcell_array_1rw_1r_test.py
Fixed local bitcell array for single and dual port
2020-08-27 14:03:05 -07:00
15_local_bitcell_array_test.py
Separate get_ and get_all for bitlines and wordlines
2020-08-25 17:08:48 -07:00
16_control_logic_multiport_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
16_control_logic_r_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
16_control_logic_rw_test.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
16_control_logic_w_test.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
18_port_address_1rw_1r_test.py
Change port_address test to 256 for riscv
2020-06-23 15:40:00 -07:00
18_port_address_test.py
Variable zjog. 512 port address test. s8 port address working.
2020-06-04 16:01:32 -07:00
18_port_data_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
18_port_data_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
18_port_data_test.py
Split port data test into single and multi-port.
2020-04-20 14:26:44 -07:00
18_port_data_wmask_1rw_1r_test.py
made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test
2020-06-23 18:16:14 -07:00
18_port_data_wmask_test.py
Update port data wmask tests
2020-06-15 06:05:05 -07:00
19_bank_select_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
19_bank_select_test.py
split pbitcell tests
2020-04-17 12:26:18 -07:00
19_multi_bank_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
19_pmulti_bank_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
19_psingle_bank_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
19_single_bank_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
19_single_bank_1w_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
19_single_bank_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
19_single_bank_test.py
Thin-cell decoder changes.
2020-05-29 10:36:07 -07:00
19_single_bank_wmask_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
19_single_bank_wmask_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_psram_1bank_2mux_1rw_1w_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_psram_1bank_2mux_1rw_1w_wmask_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_psram_1bank_2mux_1w_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_psram_1bank_2mux_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_psram_1bank_4mux_1rw_1r_test.py
Unskip 20_psram_1bank_4mux_1rw_1r_test
2020-06-09 16:04:39 -07:00
20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
20_sram_1bank_2mux_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_sram_1bank_2mux_1w_1r_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
20_sram_1bank_2mux_1w_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_sram_1bank_2mux_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_1bank_2mux_wmask_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
20_sram_1bank_2mux_wmask_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_1bank_4mux_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_1bank_8mux_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_sram_1bank_8mux_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_1bank_32b_1024_wmask_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
20_sram_1bank_nomux_1rw_1r_test.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
20_sram_1bank_nomux_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
20_sram_1bank_nomux_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_1bank_nomux_wmask_sparecols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
20_sram_1bank_nomux_wmask_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
20_sram_2bank_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
21_hspice_delay_test.py
Update golden results with new lib syntax
2020-04-22 10:40:04 -07:00
21_hspice_setuphold_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
21_model_delay_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
21_ngspice_delay_extra_rows_test.py
New lib syntax for golden results
2020-05-02 09:44:56 +00:00
21_ngspice_delay_test.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
21_ngspice_setuphold_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_psram_1bank_2mux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_psram_1bank_4mux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_psram_1bank_8mux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_psram_1bank_nomux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_sram_1bank_2mux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_sram_1bank_2mux_sparecols_func_test.py
SRAM layout and functional tests with spare cols
2020-06-03 12:31:30 +00:00
22_sram_1bank_4mux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_sram_1bank_8mux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_sram_1bank_nomux_1rw_1r_func_test.py
Rename tests for consistency
2020-06-19 08:53:35 -07:00
22_sram_1bank_nomux_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
22_sram_1bank_nomux_sparecols_func_test.py
SRAM layout and functional tests with spare cols
2020-06-03 12:31:30 +00:00
22_sram_1bank_wmask_1rw_1r_func_test.py
Rename tests for consistency
2020-06-19 08:53:35 -07:00
22_sram_wmask_func_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
23_lib_sram_model_corners_test.py
Nominal corner only for sim tests. Netlist only for speed.
2019-11-30 12:48:25 -08:00
23_lib_sram_model_test.py
Nominal corner only for sim tests. Netlist only for speed.
2019-11-30 12:48:25 -08:00
23_lib_sram_prune_test.py
Nominal corner only for sim tests. Netlist only for speed.
2019-11-30 12:48:25 -08:00
23_lib_sram_test.py
Nominal corner only for sim tests. Netlist only for speed.
2019-11-30 12:48:25 -08:00
24_lef_sram_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
25_verilog_sram_test.py
Netlist only in verilog test
2020-04-02 12:43:19 -07:00
26_hspice_pex_pinv_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
26_ngspice_pex_pinv_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
26_pex_test.py
Make unit test configs generic to tech_name
2019-11-17 00:44:31 +00:00
30_openram_back_end_test.py
Remove dynamic bitcell multiple detection.
2020-04-09 11:38:18 -07:00
30_openram_front_end_test.py
Remove dynamic bitcell multiple detection.
2020-04-09 11:38:18 -07:00
50_riscv_func_test.py
Skip riscv func test for time sake
2020-06-26 06:50:45 -07:00
50_riscv_phys_test.py
Skip phys riscv test
2020-06-25 17:31:23 -07:00
b3v3_1check.log
single port progess
2020-09-14 18:11:38 -07:00
diff
single port progess
2020-09-14 18:11:38 -07:00
missing_pin.gds
rep col done w/o power pins
2020-09-23 06:24:52 -07:00
regress.py
Full path to skip tests file
2020-06-10 10:23:05 -07:00
skip_tests_sky130.txt
Skip and4_dec test
2020-06-23 10:08:28 -07:00
sram_1b_16_1rw_freepdk45.log
single port progess
2020-09-14 18:11:38 -07:00
sram_1b_16_1rw_s8.log
single port progess
2020-09-14 18:11:38 -07:00
sram_1b_16_1rw_scn4m_subm.log
replica col arrangement done
2020-09-23 04:51:09 -07:00
sram_1b_16_1rw_sky130.log
rep col done w/o power pins
2020-09-23 06:24:52 -07:00
sram_1rw_1r_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_wmask_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
testutils.py
Fail unit test, but mention if LVS passes and DRC fails.
2020-06-30 16:22:44 -07:00