 Matt Guthaus
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5d59863efc
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Fix p_en_bar at top level. Change default scn4m period to 10ns.
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2018-11-27 14:44:55 -08:00 |
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Matt Guthaus
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c45f990413
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Change en to en_bar in precharge. Fix logic for inverted p_en_bar.
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2018-11-27 14:17:55 -08:00 |
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Matt Guthaus
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0c286d6c29
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Revert to 5V example until we fix spice models in scn4m_subm
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2018-11-27 14:17:06 -08:00 |
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 Jesse Cirimelli-Low
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5aa8c46c16
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Merge branch 'dev' into datasheet_gen
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2018-11-27 13:54:21 -08:00 |
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Matt Guthaus
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bf31126679
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Correct decoder output numbers to follow address order
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2018-11-27 12:03:13 -08:00 |
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Matt Guthaus
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b912f289a6
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Remove extra X in instance names
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2018-11-27 12:02:53 -08:00 |
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Matt Guthaus
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2237af0463
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Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix
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2018-11-26 18:01:34 -08:00 |
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 Matt Guthaus
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cf23eacd0e
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Add wl_en
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2018-11-26 18:00:59 -08:00 |
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Matt Guthaus
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21759d59b4
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Remove inverter in wordline driver
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2018-11-26 16:41:31 -08:00 |
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Matt Guthaus
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9e0b31d685
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Make pand2 and pbuf derive pgate. Initial DRC wrong layout.
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2018-11-26 16:19:18 -08:00 |
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Matt Guthaus
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dd79fc560b
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Corretct modules for add_inst
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2018-11-26 15:35:29 -08:00 |
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Matt Guthaus
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b440031855
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Add netlist only mode to new pgates
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2018-11-26 15:29:42 -08:00 |
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Matt Guthaus
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2eff166527
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Rotate vias in pand2
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2018-11-26 14:05:04 -08:00 |
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Matt Guthaus
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5209619987
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Move pnand2 output to allow input pin access on M2
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2018-11-26 13:59:53 -08:00 |
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Matt Guthaus
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8fba32ca12
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Add pand2 draft
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2018-11-26 13:45:22 -08:00 |
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 Jennifer Eve Sowash
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524334d24d
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Merge branch 'dev' into pdriver
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2018-11-26 13:15:47 -08:00 |
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 Hunter Nichols
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b06aa84824
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Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips.
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2018-11-23 18:55:15 -08:00 |
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Hunter Nichols
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5f954689a5
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In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes.
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2018-11-23 13:19:55 -08:00 |
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Jennifer Eve Sowash
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bb7773ca7f
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Editted pbuf.py to pass regression.
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2018-11-20 14:39:11 -08:00 |
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Jesse Cirimelli-Low
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29f19ad70f
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replaced absolute links with relative links
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2018-11-20 12:27:54 -08:00 |
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Jesse Cirimelli-Low
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7d070c2652
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Added links to logos
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2018-11-20 11:51:38 -08:00 |
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Hunter Nichols
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67977bab3e
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Fixed port issue in bank. Changed golden data due to netlist change.
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2018-11-20 11:39:14 -08:00 |
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Jesse Cirimelli-Low
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1942ef33ac
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Merge branch 'dev' into datasheet_gen
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2018-11-20 11:23:42 -08:00 |
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Hunter Nichols
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62cbbca852
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Merged, fixed conflict bt matching control logic creation to dev.
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2018-11-19 22:20:20 -08:00 |
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Hunter Nichols
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2f29ad5510
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Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed.
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2018-11-19 22:13:58 -08:00 |
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Matt Guthaus
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b8299565eb
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Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
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2018-11-19 17:32:55 -08:00 |
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Hunter Nichols
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8257e4fe8c
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Changed syntax in replica_bl tests, golden data to fit new values in delay tests.
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2018-11-19 16:51:43 -08:00 |
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Matt Guthaus
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20d4e390f6
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Add bounding box of connector for when there are multiple connectors
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2018-11-19 15:45:07 -08:00 |
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Matt Guthaus
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2694ee1a4c
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Add all insufficient grids that overlap the pin at all
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2018-11-19 15:43:19 -08:00 |
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Hunter Nichols
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e8f1c19af6
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Merge branch 'dev' into multiport_characterization
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2018-11-19 15:42:48 -08:00 |
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Matt Guthaus
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a47509de26
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Move via away from cell edges
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2018-11-19 15:42:22 -08:00 |
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Hunter Nichols
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a55d907d03
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High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME
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2018-11-19 15:40:26 -08:00 |
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Matt Guthaus
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6a7d721562
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Add new bbox routine for pin enclosures
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2018-11-19 09:28:29 -08:00 |
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Matt Guthaus
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4630f52de2
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Use array ur instead of bank ur to pace row addr dff
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2018-11-19 08:41:26 -08:00 |
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Hunter Nichols
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d3c47ac976
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Made delay measurements less dependent on period.
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2018-11-18 23:28:49 -08:00 |
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Matt Guthaus
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7709d5caa7
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Move row addr dffs to top of bank to prevent addr route problems
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2018-11-18 10:02:08 -08:00 |
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Matt Guthaus
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ba8bec3f67
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Two m1 pitches at top of control logic
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2018-11-18 09:30:27 -08:00 |
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Matt Guthaus
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c677efa217
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Fix control logic center location. Fix rail height error in write only control logic.
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2018-11-18 09:15:03 -08:00 |
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Hunter Nichols
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3716030a23
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Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts.
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2018-11-16 16:57:22 -08:00 |
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Matt Guthaus
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047d6ca2ef
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Must channel rout the column mux bits since they could overlap
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2018-11-16 16:21:31 -08:00 |
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Matt Guthaus
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b89c011e41
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Add psram 1w/1r test. Fix bl/br port naming errors in bank.
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2018-11-16 15:31:22 -08:00 |
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Matt Guthaus
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8f28f4fde5
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Don't always add all 3 types of contorl. Add write and read only port lists.
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2018-11-16 15:03:12 -08:00 |
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Matt Guthaus
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b13d938ea8
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Add m3m4 short hand in design class
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2018-11-16 14:10:49 -08:00 |
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Matt Guthaus
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4997a20511
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Must set library cell flag for netlist only mode as well
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2018-11-16 13:37:17 -08:00 |
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Matt Guthaus
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ca750b698a
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Uniquify bitcell array
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2018-11-16 12:52:22 -08:00 |
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Matt Guthaus
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e040fd12f9
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Bitcell and bitcell array can be named the same.
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2018-11-16 12:00:23 -08:00 |
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Matt Guthaus
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5e0eb609da
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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Matt Guthaus
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68ac7e5955
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Fix offset of column decoder with new mirroring
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2018-11-15 17:27:58 -08:00 |
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Matt Guthaus
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712b71c5ca
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Mirror port 1 column decoder in X and Y
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2018-11-15 15:26:59 -08:00 |
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Jennifer Eve Sowash
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c73004de35
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Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver
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2018-11-15 14:06:38 -08:00 |
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