Hunter Nichols b06aa84824 Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips.

2018-11-23 18:55:15 -08:00

..

base

Use grid furthest from blockages when blocked pin. Enclose multiple connectors.

2018-11-19 17:32:55 -08:00

bitcells

Merged with dev. Fixed merge conflict.

2018-11-09 17:18:19 -08:00

characterizer

Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips.

2018-11-23 18:55:15 -08:00

datasheet

moved flask_table warning from sram.py to datasheet_gen.py

2018-10-18 09:58:19 -07:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

modules

Fixed port issue in bank. Changed golden data due to netlist change.

2018-11-20 11:39:14 -08:00

pgates

Separated relative delay into rise/fall.

2018-11-14 23:34:53 -08:00

router

Use grid furthest from blockages when blocked pin. Enclose multiple connectors.

2018-11-19 17:32:55 -08:00

tests

Fixed port issue in bank. Changed golden data due to netlist change.

2018-11-20 11:39:14 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Add magic/netgen to example config

2018-11-07 13:54:00 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fix date/time formatting to remove fraction seconds.

2018-11-14 10:31:33 -08:00

Makefile

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openram.py

Merge branch 'dev' into supply_routing

2018-10-20 14:29:19 -07:00

options.py

Add new option to enable inline checks at each level of hierarchy. Default is off.

2018-11-13 16:51:19 -08:00

sram_1bank.py

Use array ur instead of bank ur to pace row addr dff

2018-11-19 08:41:26 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

sram_base.py

Merged, fixed conflict bt matching control logic creation to dev.

2018-11-19 22:20:20 -08:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes.

2018-11-23 13:19:55 -08:00