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OpenRAM
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3,756 Commits 4 Branches 63 Tags 78 MiB
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375 Commits

Author SHA1 Message Date
mrg 47690e0076 Merge branch 'dev' into docker 2021-12-29 14:42:32 -08:00
Jesse Cirimelli-Low cf8c486cea merge sky130_dummy_array 2021-12-22 16:00:59 -08:00
Jesse Cirimelli-Low de60a1c38a merge in opc fixes 2021-12-22 15:53:36 -08:00
Jesse Cirimelli-Low 468de963f6 remove add_mod in sky130 2021-12-22 15:51:49 -08:00
Jesse Cirimelli-Low c24c37a15a Merge branch 'dev' into lvs 2021-12-22 15:46:09 -08:00
Jesse Cirimelli-Low 8a0450afac adjust replica col wls 2021-12-22 15:46:03 -08:00
Jesse Cirimelli-Low 8879820af4 replica col lvs fix 2021-12-15 14:19:52 -08:00
Jesse Cirimelli-Low 4e5744df50 remove add_mod() 2021-12-15 01:36:56 -08:00
Jesse Cirimelli-Low 99981109e8 Merge branch 'dev' into opc_fix 2021-12-15 01:31:21 -08:00
Jesse Cirimelli-Low ddb76c4aff fix dummy array opc 2021-12-15 01:28:30 -08:00
Jesse Cirimelli-Low 8eb6caa248 fix bitcell array opc errors 2021-12-14 22:15:27 -08:00
mrg d8d8636d0f Comment out calibre in freepdk45 2021-11-22 15:54:22 -08:00
mrg 66c9501621 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg fc0516460d Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg 32c7e90662 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 48e35588f4 Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg bfb33ecbb4 Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 779d6ad2b2 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
mrg 735f9cf450 Remove klayout from scmos 2021-11-22 11:33:27 -08:00
mrg 552811b41b Use klayout in SCMOS too. 2021-11-22 11:33:27 -08:00
mrg b7362ba011 Do not run same well spacing for backwards compatibility. Add pbitcell cheat. 2021-11-22 11:33:27 -08:00
mrg 43bbd2e722 Fixed incorrect via2 spacing rule in tech file. 2021-11-22 11:33:27 -08:00
mrg 8f296810be Fix cheat on wordline driver name. 2021-11-22 11:33:27 -08:00
mrg 6ee4697711 Change cell names in lvs file 2021-11-22 11:33:27 -08:00
mrg 5d33db0ee4 Add write driver to well connect list 2021-11-22 11:33:27 -08:00
mrg 5dc885a674 Update nwell spacing to be same potential 2021-11-22 11:33:27 -08:00
mrg 2e846cb22f Fix regexes for cells without well taps 2021-11-22 11:33:27 -08:00
mrg acc9b2d223 Connect pwell and bulk when no tap 2021-11-22 11:33:27 -08:00
mrg 141b42dc0e Add DRC rules and display files 2021-11-22 11:33:27 -08:00
mrg 7d7ffe76e0 Debugging klayout for SCMOS and FreePDK45. 2021-11-22 11:33:27 -08:00
mrg f764ac446c Use Caravel-like sky130 install path with ngspice models. 2021-11-17 13:19:23 -08:00
mrg 968a233b82 Don't install in share/pdk 2021-11-08 09:31:56 -08:00
mrg c102ed728c Move tests to test Makefile 2021-11-03 11:36:19 -07:00
mrg af67b738af Add ability to run a single unit test in docker 2021-11-03 08:32:29 -07:00
mrg d7a20bc69b Debug initial docker run scripts 2021-11-02 15:07:18 -07:00
mrg fa2232fc11 Initial commit of sky130 config files 2021-10-04 15:16:28 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols bd57a043d7 Removed reference to lamba in freepdk45 tech file. Fixed issue with transconductance equation. 2021-09-20 16:51:02 -07:00
mrg f2882782e7 Use calibre by default until klayout LVS is clean. 2021-09-20 11:05:49 -07:00
mrg 10753a0802 Change via2 to 65nm to be compatible with Calibre FreePDK45 deck 2021-09-16 15:42:02 -07:00
mrg 0a91bd01c8 Fix DRC and LVS scripts 2021-09-16 15:37:26 -07:00
mrg 8081bea708 Shrink 70nm contacts to 65nm 2021-09-16 15:28:39 -07:00
mrg c5f372c264 Fix via2 to match incorrect FreePDK45 rules 2021-09-15 11:58:31 -07:00
mrg f3d1c6edc3 klayout DRC/LVS working 2021-09-15 11:33:39 -07:00
mrg 554b3f4ca7 Initial klayout DRC/LVS options 2021-09-07 16:51:16 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols de2dae4030 Changed unit capacitance from CACTI estimation to PTM estimation. 2021-08-25 15:23:12 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
mrg c117238fa7 Initial klayout DRC/LVS options 2021-08-03 14:41:09 -07:00