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OpenRAM
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2,121 Commits 4 Branches 63 Tags 78 MiB
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2121 Commits

Author SHA1 Message Date
jcirimel 0f9e38881c update stim for large pex layouts 2020-05-04 03:05:33 -07:00
jcirimel 89688f8ea9 fix pex for larger memories 2020-05-04 01:31:51 -07:00
Jesse Cirimelli-Low 6e070925b6 update magic for multiport 2020-01-28 02:32:34 +00:00
Jesse Cirimelli-Low 30604fb093 add multiport support for pex labels 2020-01-28 00:28:55 +00:00
Jesse Cirimelli-Low 1a97dfc63e syncronize bitline naming convention betwen bitcell and pbitcell 2020-01-27 11:50:43 +00:00
Jesse Cirimelli-Low d42cd9a281 pbitcell working with bitline adjustments 2020-01-27 10:03:31 +00:00
Jesse Cirimelli-Low 1062cbfd7f begin fixes to pbitcell, prepare multibank pex 2020-01-24 10:24:29 +00:00
jcirimel 40c01dab85 fix bl in stim file 2020-01-21 01:44:15 -08:00
jcirimel 73691f6054 fix bug in top level bitline label placement 2020-01-21 00:20:52 -08:00
Jesse Cirimelli-Low 5778901cfe pull bitline labels to top level spice 2020-01-20 12:16:30 +00:00
jcirimel 364842569a fix s_en in stim 2020-01-16 12:16:49 -08:00
jcirimel 075bf0d841 label bitcell in stim, add s_en top level to stim 2020-01-16 03:51:29 -08:00
Jesse Cirimelli-Low 2733c3bf3f fix custom bitcell labeling; fix gds scaling in labeling 2020-01-15 09:00:02 +00:00
Jesse Cirimelli-Low 05ab018ffc strip padding character from gds reading 2020-01-07 00:01:32 +00:00
Jesse Cirimelli-Low 3ab99d7f9c update gds library, generalize geometry reverse transform function 2019-12-24 05:01:55 +00:00
Jesse Cirimelli-Low 5b44dce50d added labels to scn4m magic libaries 2019-12-23 02:22:11 +00:00
Jesse Cirimelli-Low 88d3da0b4a fix control logic pex labels with multiport 2019-12-18 12:45:12 +00:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matthew Guthaus 04af5480d2 Add skeleton files for pwrite_driver 2019-10-30 21:34:03 +00:00
Hunter Nichols e4b490051d Adjusted vth0 of FF and SS models in scn4m from nominal. 2019-10-07 15:26:20 -07:00
Matt Guthaus ccc6a67021 Update version to 1.1.2 2019-10-07 12:28:02 -07:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
Matt Guthaus 76ad2e68c0 Update slack invite link. 2019-10-06 17:28:06 +00:00
vagrant 67c768d22c Refactor bitcell to bitcell_base. Pep8 format bitcells. 2019-10-06 01:08:23 +00:00
Hunter Nichols d722311822 Merge branch 'dev' into update_scmos_models 2019-10-03 13:16:32 -07:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Hunter Nichols b420f77ff1 Updated leakage power golden data in hspice delay test. 2019-10-01 15:26:34 -07:00
Hunter Nichols 19a09470d4 Merged with dev, conflict in golden data of hspice delay test. 2019-10-01 14:26:34 -07:00
Hunter Nichols 1bdd9f56d6 Changed scn4m tau and parasitic model values to account for spice model changes. 2019-09-30 14:22:34 -07:00
Hunter Nichols 7b029a4582 Updated golden values in delay tests due to model changes. 2019-09-30 14:02:00 -07:00
Matt Guthaus b0dcfb5b2d Fix leakage mismatch in results. 2019-09-27 15:14:01 -07:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus cbbcb97a10 Merge branch 'dev' into feedthru 2019-09-27 09:42:51 -07:00
Hunter Nichols 84d41dd380 Replaced scn4m models. FF/SS are duplicated from nominal models. 2019-09-26 23:45:36 -07:00
jsowash a9a44028e6 Merged dev into add_wmask. 2019-09-25 18:08:41 -07:00
Matt Guthaus 4d9cca7360 Remove setup_scripts from README.md 2019-09-16 13:12:00 -07:00
Matt Guthaus 76e8487e71 Update README to point to OpenRAM for badges. 2019-09-16 13:09:40 -07:00
Matt Guthaus 142044df55 Update README.md 2019-09-14 11:35:15 -07:00
Matt Guthaus 99507ba5c5 Remove rbl_bl_delay_bar from w_en logic inputs. 2019-09-07 23:22:01 -07:00
Matt Guthaus 9ec663e0b1 Write all write ports first cycle. Don't check feedthru. 2019-09-07 20:20:44 -07:00
Matt Guthaus 35a8dd2eec Factor out masking function 2019-09-07 20:05:05 -07:00
Matt Guthaus 322af0ec09 Remove sense enable during writes 2019-09-07 20:04:48 -07:00
Matt Guthaus e5db02f7d8 Fix wrong function. Except unknown ports. 2019-09-06 14:59:23 -07:00
Matt Guthaus 93c89895c9 Remove unused test structures 2019-09-06 14:58:47 -07:00
Matt Guthaus b5b0e35c8a Fix syntax error. 2019-09-06 12:29:28 -07:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00
Matt Guthaus 6bee66f9dc Forgot to add cs_bar to rw port rails. 2019-09-06 09:29:23 -07:00
Matt Guthaus 969cca28e4 Enable sensing during writes. Need to add dedicated test. 2019-09-06 07:16:50 -07:00
jsowash 1c65b90c70 Merge branch 'dev' into add_wmask 2019-09-05 09:15:05 -07:00
Matt Guthaus 678b2cc3fa Fix functional test clk name 2019-09-04 18:59:08 -07:00