mirror of https://github.com/VLSIDA/OpenRAM.git
Changed scn4m tau and parasitic model values to account for spice model changes.
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@ -291,8 +291,8 @@ spice["dff_leakage"] = 1 # Leakage power of flop in nW
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spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
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#Logical Effort relative values for the Handmade cells
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parameter["le_tau"] = 23 #In pico-seconds.
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parameter["min_inv_para_delay"] = .73 #In relative delay units
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parameter["le_tau"] = 18.17 #In pico-seconds.
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parameter["min_inv_para_delay"] = 2.07 #In relative delay units
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parameter["cap_relative_per_ff"] = .91 #Units of Relative Capacitance/ Femto-Farad
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parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
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parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
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