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Author	SHA1	Message	Date
Jacob Walker	09f9c4cc20	some rom bank cleanup	2023-03-30 11:30:50 -07:00
mrg	56e14113aa	Change rom_base_bank name and top pin names	2023-03-30 11:30:50 -07:00
mrg	d2b5be0130	Add exclude tests for ROMs	2023-03-30 11:30:50 -07:00
mrg	fe65a20431	Rename ROM unit tests.	2023-03-30 11:30:50 -07:00
mrg	041c738cb2	Rework macros to run ROM tests too.	2023-03-30 11:30:50 -07:00
Jacob Walker	eec0f02bb8	skip test file	2023-03-30 11:30:50 -07:00
Jacob Walker	b50ec272da	updated top level rom unit tests	2023-03-30 11:30:50 -07:00
Jacob Walker	cd2314f008	better name	2023-03-30 11:30:50 -07:00
Jacob Walker	879c14b828	sky130 only	2023-03-30 11:30:50 -07:00
Jacob Walker	577cdcb232	example configs	2023-03-30 11:30:50 -07:00
Jacob Walker	41f0b9a412	rom compiler top level	2023-03-30 11:30:50 -07:00
Jacob Walker	2d5199961d	revert changes to pinvbuf	2023-03-30 11:30:50 -07:00
Jacob Walker	382c91f342	precharge array test passing sky130	2023-03-30 11:30:50 -07:00
Jacob Walker	92251fe61e	more code cleaning	2023-03-30 11:30:50 -07:00
Jacob Walker	90cf382a43	removed hardcoded DRC rule	2023-03-30 11:30:50 -07:00
Jacob Walker	0cb4459b4b	changed ROM test data path	2023-03-30 11:30:50 -07:00
Jacob Walker	af0209ec96	passing code style	2023-03-30 11:30:50 -07:00
Jacob Walker	79efff9ca6	code cleanup and updated copyright	2023-03-30 11:30:50 -07:00
Jacob Walker	ab955f0da8	removed data files	2023-03-30 11:30:50 -07:00
Jacob Walker	bbf2cd2913	Changes for test generation and simulation	2023-03-30 11:30:50 -07:00
Jacob Walker	89c7d50bd1	added row of nmos to end of array for precharge	2023-03-30 11:30:50 -07:00
SWalker	f847721500	changes to control logic, invert polarity of precharge	2023-03-30 11:30:50 -07:00
SWalker	9cefe5da7c	added unrouted output buffers	2023-03-30 11:30:50 -07:00
SWalker	764601a721	added binning to precharge pmos	2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low	6981cfa58b	add example of writing out simulation netlist	2023-03-30 11:30:50 -07:00
Jacob Walker	a64361b9d1	testing data for rom tests	2023-03-30 11:30:50 -07:00
Jacob Walker	736bd51fe1	add top level pins for sim	2023-03-30 11:30:50 -07:00
Jacob Walker	81bf2d7ae7	fixed decode lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	16df8e0e43	fixing decoder lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	559300e5cc	taps in main array and decoder	2023-03-30 11:30:50 -07:00
Jacob Walker	f7aed247fd	column control and address precharge	2023-03-30 11:30:50 -07:00
Jacob Walker	ce8197d206	pitch match decoder and array	2023-03-30 11:30:50 -07:00
Jacob Walker	e697efa5f6	fixed base array lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	b2631b60ff	updated imports to match upstream dev openram	2023-03-30 11:30:50 -07:00
Jacob Walker	63925bd48e	Decoder array and start of rom bank	2023-03-30 11:30:50 -07:00
Jacob Walker	bc8d564dbf	array with poly straps passing drc/lvs	2023-03-30 11:30:50 -07:00
Jacob Walker	aea3c0ad01	passing drc/lvs on 4x4 rom array	2023-03-30 11:30:50 -07:00
Jacob Walker	a3e271f6fb	reoriented cell and added tap cell	2023-03-30 11:30:50 -07:00
Jacob Walker	7309af7e29	base and dummy array alignment in sky130	2023-03-30 11:30:50 -07:00
Jacob Walker	d7ac26a053	array generation and bitline routing with array module	2023-03-30 11:30:50 -07:00
Jacob Walker	4db5c3be26	basic nmos array, for nand rom	2023-03-30 11:30:50 -07:00
vlsida-bot	20ca8e3b22	Bump version: 1.2.6 -> 1.2.7 v1.2.7	2023-03-16 23:46:12 +00:00
Eren Dogan	f62ca94ad4	Cleanup debug.md	2023-03-16 15:20:26 -07:00
Eren Dogan	c166a50f21	Update debugging documentation	2023-03-16 15:04:58 -07:00
Eren Dogan	6eebef8c72	Fix typo in Makefile	2023-03-16 14:40:24 -07:00
Eren Dogan	c8b5b81bd8	Cleanup documentation	2023-03-16 14:10:22 -07:00
vlsida-bot	0fe8b3be17	Bump version: 1.2.5 -> 1.2.6 v1.2.6	2023-03-15 21:08:20 +00:00
Eren Dogan	9873b4cdf9	Fix Python version in documentation	2023-03-15 12:41:50 -07:00
Eren Dogan	4994e3ddde	Move library documentation to its own page	2023-03-15 12:40:04 -07:00
Eren Dogan	c0d9941985	Cleanup README	2023-03-14 21:38:35 -07:00