2211 Commits

Author	SHA1	Message	Date
mrg	098219d56c	Add npc enclosure to poly contacts	2020-06-11 11:53:59 -07:00
mrg	f973dd6a5c	Save LVS model with no u too for Calibre	2020-06-11 11:53:34 -07:00
mrg	dff28a9997	Merge branch 'tech_migration' into dev	2020-06-10 17:09:05 -07:00
mrg	196e5998c8	Half poly space per cell at top and bottom.	2020-06-10 16:52:51 -07:00
mrg	fdf92d0da1	Rename test 14	2020-06-10 16:41:26 -07:00
mrg	0b4b5e7133	More exact input spacing in pnand3	2020-06-10 16:19:24 -07:00
mrg	bfd1abc79f	Replica column pins start at 0 height.	2020-06-10 14:58:55 -07:00
mrg	469cd260b9	Change bitcell array name to match	2020-06-10 14:54:20 -07:00
mrg	f2c45a230e	Add new replica column test. Add more skip tests.	2020-06-10 11:00:00 -07:00
mrg	10be2d08b5	Full path to skip tests file	2020-06-10 10:23:05 -07:00
mrg	5e3332453b	Allow power pins to start on any layer besides m1	2020-06-10 10:15:23 -07:00
mrg	c119e60e79	Add more s8 skip tests	2020-06-10 10:14:52 -07:00
mrg	d4fc88124a	Rename dff_buf test	2020-06-09 17:18:19 -07:00
mrg	064fe34edf	Fix pinvbuf layers	2020-06-09 17:16:35 -07:00
mrg	14782914b3	Remove vertical pand gates	2020-06-09 16:40:59 -07:00
mrg	e6babc301d	Incrase space for pnand gates	2020-06-09 16:34:15 -07:00
mrg	c6b875146d	Use local skip file	2020-06-09 16:33:59 -07:00
mrg	fd49d3ed6a	Add tech specific skip tests for making new techs.	2020-06-09 16:09:15 -07:00
mrg	580b0601b5	Unskip 20_psram_1bank_4mux_1rw_1r_test	2020-06-09 16:04:39 -07:00
mrg	a28e747a02	Fix precharge offset. Move well rules to design class.	2020-06-09 15:28:50 -07:00
mrg	148521c458	Remove stdc layer	2020-06-09 13:48:47 -07:00
mrg	157926960b	Flip freepdk45 flop, dff_buf route layer change	2020-06-09 13:48:16 -07:00
mrg	8c6d5b49be	Consider diffusion spacing in active offset	2020-06-09 13:09:52 -07:00
mrg	77fb7017c4	Merge branch 'tech_migration' into dev	2020-06-08 12:54:41 -07:00
mrg	9cc36c6d3a	Bus code converted to pins. Fix layers on control signal routes in bank.	2020-06-08 11:01:14 -07:00
Aditi Sinha	c39c0efd39	Updated spare col tests	2020-06-08 16:38:18 +00:00
Aditi Sinha	300522a1a8	Change spare enable pins offset to lower right	2020-06-08 14:31:46 +00:00
Aditi Sinha	ef940e0dc5	Fixes for functional test of spare cols	2020-06-08 05:02:04 +00:00
Aditi Sinha	d5041afebc	Merge branch 'dev' into bisr	2020-06-07 16:27:25 +00:00
jcirimel	5d5ed552e3	Merge branch 'dev' into discrete_models	2020-06-06 01:48:06 -07:00
mrg	0837432d45	Wordline route layers and (optional) via.	2020-06-05 16:47:22 -07:00
jcirimel	9857a3f7e7	Merge branch 'dev' into discrete_models	2020-06-05 16:47:01 -07:00
mrg	5514996708	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
mrg	00b51f5464	PEP8 format replica_bitcell_array	2020-06-05 13:49:32 -07:00
mrg	4fef632dce	Fix syntax error	2020-06-05 12:13:41 -07:00
mrg	a62b85a6b1	Update mirroring in port_data for bitcell mirrored arrays	2020-06-05 11:29:31 -07:00
mrg	2e7f9395f2	Rename 05 test to 14	2020-06-05 09:57:16 -07:00
mrg	68ffb94d2e	Rename 05 test to 14	2020-06-05 09:55:57 -07:00
mrg	fb3acae908	PEP8 format testutils.	2020-06-05 09:44:30 -07:00
jcirimel	08f6bd8d24	optimize tx binning for area	2020-06-05 02:53:03 -07:00
mrg	e14deff3d1	Fixed offset in port_data	2020-06-04 16:03:39 -07:00
mrg	2fcecb7227	Variable zjog. 512 port address test. s8 port address working.	2020-06-04 16:01:32 -07:00
mrg	e06dc3810a	Move precharge pin to bottom	2020-06-04 12:12:19 -07:00
mrg	717188f85c	Change L shape of rbl route	2020-06-04 11:03:39 -07:00
mrg	7aafa43897	Connect RBL to bottom of precharge cell	2020-06-04 10:22:52 -07:00
mrg	249b5355ba	Adjust rbl route	2020-06-03 17:08:04 -07:00
mrg	77c95b28da	Rename precharge test	2020-06-03 16:39:46 -07:00
mrg	3927c62e32	Undo extra space due to nwell spacing	2020-06-03 16:39:33 -07:00
mrg	b2b7e7800b	Undo same bitline pitch	2020-06-03 16:39:05 -07:00
mrg	4183638f03	Align precharge bitlines with col mux	2020-06-03 16:05:57 -07:00