OpenRAM/compiler
mrg e06dc3810a Move precharge pin to bottom 2020-06-04 12:12:19 -07:00
..
base keep dev routing changes to hierarchy_layout 2020-06-03 12:54:15 -07:00
bitcells merge conflict - port data 2020-06-02 14:15:39 -07:00
characterizer Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
custom Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
datasheet
drc PEP8 cleanup 2020-04-15 11:24:28 -07:00
example_configs
gdsMill
modules Connect RBL to bottom of precharge cell 2020-06-04 10:22:52 -07:00
pgates Move precharge pin to bottom 2020-06-04 12:12:19 -07:00
router Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
sram Change L shape of rbl route 2020-06-04 11:03:39 -07:00
tests Rename precharge test 2020-06-03 16:39:46 -07:00
verify Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
Makefile
debug.py
gen_stimulus.py
globals.py Merge remote-tracking branch 'public/dev' into dev 2020-04-22 09:28:25 -07:00
openram.py
options.py merge conflict - port data 2020-06-02 14:15:39 -07:00
run_profile.sh
sram_factory.py SRAM factory uses default name for first instance even if it has arguments. 2020-06-01 16:46:22 -07:00
view_profile.py