mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working.

2020-06-04 16:01:32 -07:00

..

base

Variable zjog. 512 port address test. s8 port address working.

2020-06-04 16:01:32 -07:00

bitcells

merge conflict - port data

2020-06-02 14:15:39 -07:00

characterizer

Merge remote-tracking branch 'public/dev' into dev

2020-04-22 09:28:25 -07:00

custom

Hard cells can accept height parameter too.

2020-06-01 16:46:00 -07:00

datasheet

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

drc

…

example_configs

revert example scn4m to non netlist only

2020-02-09 23:52:11 -08:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Variable zjog. 512 port address test. s8 port address working.

2020-06-04 16:01:32 -07:00

pgates

Move precharge pin to bottom

2020-06-04 12:12:19 -07:00

router

…

sram

Change L shape of rbl route

2020-06-04 11:03:39 -07:00

tests

Variable zjog. 512 port address test. s8 port address working.

2020-06-04 16:01:32 -07:00

verify

Don't force check in lib characterization. PEP8 formatting.

2020-04-02 12:52:42 -07:00

debug.py

…

gen_stimulus.py

…

globals.py

…

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

…

options.py

…

run_profile.sh

…

sram_factory.py

…

view_profile.py

…