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OpenRAM
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187 Commits

Author SHA1 Message Date
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
jcirimel b18e2eae8d remove debug lines and merge 2021-02-09 20:53:23 -08:00
jcirimel dbe8a7f1af fix pwell pin shape bug 2021-02-09 20:51:50 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 4b1c359089 update copyright year. 2021-01-22 11:24:53 -08:00
Hunter Nichols c8e631108a Updated sim_data for scmos 2021-01-22 00:51:14 -08:00
Hunter Nichols 59200d1048 Added updated data for scmos, removed unused files. 2021-01-13 13:09:21 -08:00
Hunter Nichols d6177b34f0 Added data which includes corner as an input feature 2020-12-17 12:59:06 -08:00
Hunter Nichols f1f6a1a520 Removed windows end of line characters. 2020-12-15 12:08:31 -08:00
Hunter Nichols 06232dee8f Added leakage and slew data. Added temporary fix to model output format. 2020-12-14 14:32:10 -08:00
Hunter Nichols 25544c3974 Added similar interface to linear regression as elmore 2020-12-14 13:59:31 -08:00
Hunter Nichols b1a7e0e55b Added power data 2020-12-09 15:21:22 -08:00
Hunter Nichols 1143dbec94 Added initial scripts and data to generate analytical model 2020-11-20 12:40:04 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg a2f29e5edd Fix missing nand4_leakage #97 2020-11-12 09:48:08 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 423e2c165f Remove test cell in scn4m_subm tech.py 2020-11-03 16:38:55 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg ef310970bf Use new Google PDK lib 2020-10-12 15:46:11 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg 138cbfac15 Flatten dummy pbitcell too 2020-09-09 12:58:22 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
mrg dfb593e9b4 Add draft lyt file -- connectivity not working 2020-08-14 10:38:22 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg e69b665689 Flatten pbitcell_1 too 2020-06-02 09:31:43 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg 5f76514cf0 Remove end of line whitespace 2020-04-21 15:20:51 -07:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
Jesse Cirimelli-Low 18573c0e42 add module properties to other technologies 2020-02-05 22:25:35 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:46:14 +01:00
Bastian Koppelmann 407bd026ee tech: Make m3_stack the power_grid stack for FreePDK45/scn4m 
explicitly stating the power_grid makes people porting a new technology
aware of this option.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:38 +01:00
Jesse Cirimelli-Low 30604fb093 add multiport support for pex labels 2020-01-28 00:28:55 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Jesse Cirimelli-Low 2733c3bf3f fix custom bitcell labeling; fix gds scaling in labeling 2020-01-15 09:00:02 +00:00
Jesse Cirimelli-Low 3ab99d7f9c update gds library, generalize geometry reverse transform function 2019-12-24 05:01:55 +00:00
Jesse Cirimelli-Low 5b44dce50d added labels to scn4m magic libaries 2019-12-23 02:22:11 +00:00
Matt Guthaus a8d370ee8c Improved comments in tech files 2019-12-20 16:35:31 -08:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matthew Guthaus 8e151553e4 Update contact types. 
Use preferred directions in tech files.
Programmatically generate based on interconnect stacks.
 2019-12-17 23:45:07 +00:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Bastian Koppelmann 1380cbc50c technology: Add tech_module to all technologies 
this allows each technology to override each cell class.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:41 +01:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matthew Guthaus 7397f110c5 Add bbox for special DRC rule boundary 2019-12-05 23:14:25 +00:00
Matt Guthaus 69bb245f28 Updates to gdsMill/tech layers 
Create active and poly contact types.
Define standard cell boundary option.
DataType and PurposeLayer are the same. Text must have type 0.
Remove vector from vlsiLayout. More debug in reader.
 2019-12-04 16:12:53 -08:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus 2a912dab7a Remove unused config files 2019-11-29 12:35:35 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus b71d630643 None for layer means unused. 2019-11-26 13:34:39 -08:00
Matt Guthaus 102758881a Use layer instead of special flags for wells 2019-11-26 13:22:52 -08:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matt Guthaus ecbed870c0 Remove blockage layer. 2019-10-30 06:54:11 -07:00
Matt Guthaus 38213d998f Add separate layer and purpose pairs to tech layers. 2019-10-25 10:03:25 -07:00
Matt Guthaus 31825d9d77 Fix magicrc for multiple openram tech paths 2019-10-24 13:17:33 -07:00
Hunter Nichols e4b490051d Adjusted vth0 of FF and SS models in scn4m from nominal. 2019-10-07 15:26:20 -07:00
Hunter Nichols 1bdd9f56d6 Changed scn4m tau and parasitic model values to account for spice model changes. 2019-09-30 14:22:34 -07:00
Hunter Nichols 84d41dd380 Replaced scn4m models. FF/SS are duplicated from nominal models. 2019-09-26 23:45:36 -07:00
Matt Guthaus 4c3b171b72 Share nominal temperature and voltage. Nominal instead of typical. 2019-09-04 16:53:58 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 283183ae9f Add Metal3/Via3/Metal4 on right gds layers 2019-09-03 15:28:20 -07:00
Matt Guthaus fc0fe91bb4 Added auto-converted lyp files to use klayout for viewing results 2019-08-26 10:41:14 -07:00
jsowash 49fffcbc92 Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver. 2019-08-08 15:49:23 -07:00
jsowash 0cfa0ac755 Shortened write driver enable pin so that a write mask can be used without a col mux in layout. 2019-08-08 12:57:32 -07:00
Matt Guthaus 4b75e49302 Remove unnecessary footer in write driver 2019-08-01 08:59:41 -07:00
mrg f5804e1cbf Flatten bitcell array for LVS symmetries. 2019-07-16 11:53:20 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg 0fbfa924f7 Add other SCMOS dummy cells 2019-07-03 14:28:12 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
mrg 5c4df2410e Fix dummy row LVS issue 2019-06-14 15:06:04 -07:00
mrg 3c3456596a Add replica row with dummy cells. 2019-06-14 14:38:55 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus e071e53090 Add comments on gds units in tech files. 2019-04-30 10:13:13 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 222b07ad7a Well contact cleanup for SCMOS TSMC 0.35 2019-04-26 10:19:11 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00