mirror of https://github.com/VLSIDA/OpenRAM.git
Flatten bitcell array for LVS symmetries.
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@ -6,6 +6,7 @@ equate class {-circuit1 pfet} {-circuit2 p}
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flatten class {-circuit1 dummy_cell_6t}
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flatten class {-circuit1 dummy_cell_1rw_1r}
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flatten class {-circuit1 dummy_cell_1w_1r}
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flatten class {-circuit1 bitcell_array_0}
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flatten class {-circuit1 pbitcell_0}
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flatten class {-circuit1 pbitcell_1}
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property {-circuit1 nfet} remove as ad ps pd
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