Jesse Cirimelli-Low
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2faa067ea6
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add support for col offset to rbc; fix rba mirroring
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2023-09-12 12:12:21 -07:00 |
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Jesse Cirimelli-Low
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0034798787
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both rbl replica array working
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2023-09-11 11:23:39 -07:00 |
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vlsida-bot
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1a8c27c549
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Bump version: 1.2.34 -> 1.2.35
v1.2.35
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2023-09-09 22:09:16 +00:00 |
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Eren Dogan
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b3e1a163d0
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Fix derouting wires in the gridless router
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2023-09-09 13:32:16 -07:00 |
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Jesse Cirimelli-Low
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e553f3db41
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fix sram.sp spare_wen
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2023-09-07 12:24:39 -07:00 |
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vlsida-bot
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9c66473cc9
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Bump version: 1.2.33 -> 1.2.34
v1.2.34
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2023-09-07 06:07:59 +00:00 |
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Eren Dogan
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995cc4f60f
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Fix typo
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2023-09-06 21:38:19 -07:00 |
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Eren Dogan
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099869d4c9
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Fix typos
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2023-09-03 18:35:07 -07:00 |
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Eren Dogan
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3f2d61a0fa
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Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108)
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2023-09-03 18:21:31 -07:00 |
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Jesse Cirimelli-Low
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eb82053ab8
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copy router from dev
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2023-09-03 13:16:18 -07:00 |
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Jesse Cirimelli-Low
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5605154cc2
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merge dev
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2023-09-02 12:27:38 -07:00 |
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vlsida-bot
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1a25fcf9a5
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Bump version: 1.2.32 -> 1.2.33
v1.2.33
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2023-09-02 18:43:35 +00:00 |
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Eren Dogan
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abb12bd785
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Increase non-preferred direction cost in router
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2023-09-02 08:00:58 -07:00 |
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Eren Dogan
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775922774a
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Use bbox trees to iterate over shapes in routing region efficiently
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2023-09-01 20:37:07 -07:00 |
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Jesse Cirimelli-Low
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066d00f44b
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increase power ring crba width for drc
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2023-09-01 02:02:41 -07:00 |
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Eren Dogan
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d9004f6de6
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Print more info for the routing processes
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2023-08-31 19:03:31 -07:00 |
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Eren Dogan
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8a60684e51
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Increase the routing region inflation to be safer
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2023-08-31 18:26:45 -07:00 |
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Eren Dogan
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a9e63efad7
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Increase via cost in router
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2023-08-31 18:26:04 -07:00 |
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Jesse Cirimelli-Low
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c9a848550c
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Revert "merge dev"
This reverts commit daec840888, reversing
changes made to 29e80e8f25.
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2023-08-30 22:40:35 -07:00 |
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Jesse Cirimelli-Low
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daec840888
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merge dev
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2023-08-30 22:04:42 -07:00 |
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Jesse Cirimelli-Low
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29e80e8f25
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bump sky130 sram library
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2023-08-30 21:18:50 -07:00 |
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Jesse Cirimelli-Low
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0cba6a6050
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single port sky130 crba passing lvs
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2023-08-30 20:59:02 -07:00 |
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vlsida-bot
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b281771753
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Bump version: 1.2.31 -> 1.2.32
v1.2.32
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2023-08-30 16:52:07 +00:00 |
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Eren Dogan
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56bee27ee3
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Don't write/read gds files unnecessarily for router
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2023-08-29 21:45:52 -07:00 |
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Jesse Cirimelli-Low
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8f2e4c6914
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power ring working
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2023-08-28 22:15:05 -07:00 |
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vlsida-bot
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b525ba60a0
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Bump version: 1.2.30 -> 1.2.31
v1.2.31
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2023-08-28 21:12:21 +00:00 |
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Jesse Cirimelli-Low
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8794070ebc
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various refactor changes
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2023-08-28 12:31:55 -07:00 |
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Eren Dogan
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e12ab68362
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Simplify closest edge calculation in signal escape router
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2023-08-28 10:38:53 -07:00 |
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Eren Dogan
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fa5de05be3
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Merge branch 'dev' into gridless_router
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2023-08-27 21:17:58 -07:00 |
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Eren Dogan
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53cc99f5c1
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Perform signal escape routing in smaller regions
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2023-08-27 21:16:34 -07:00 |
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Eren Dogan
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9df3c2ac59
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Return the path in source-to-target order
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2023-08-27 21:15:25 -07:00 |
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Eren Dogan
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141a4e3380
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Don't scale the routing region if no path is found
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2023-08-27 15:42:09 -07:00 |
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Jesse Cirimelli-Low
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ba51149dce
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placement working for sp capped rba, need fix rowcap patterns
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2023-08-26 18:54:07 -07:00 |
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vlsida-bot
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0ac2922573
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Bump version: 1.2.29 -> 1.2.30
v1.2.30
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2023-08-26 22:17:23 +00:00 |
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Jesse Cirimelli-Low
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ca5ca0c7a8
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bump sram library commit to fix colenda gds
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2023-08-26 15:29:08 -05:00 |
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Jesse Cirimelli-Low
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72a7b0342b
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work on capped rba
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2023-08-25 16:39:32 -07:00 |
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Jesse Cirimelli-Low
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036cc54b99
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rba done w/o wordline
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2023-08-24 02:55:45 -07:00 |
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Jesse Cirimelli-Low
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64b0cd25d7
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replica col passing
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2023-08-22 01:16:35 -07:00 |
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Jesse Cirimelli-Low
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a05ab6e908
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route supplies + fix replica col dummy
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2023-08-22 01:09:19 -07:00 |
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Jesse Cirimelli-Low
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450f8ab0c3
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replica col generating, funny dummy cell placement
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2023-08-22 00:45:57 -07:00 |
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Jesse Cirimelli-Low
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5cf50b333a
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bitcell array passing
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2023-08-21 20:25:51 -07:00 |
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Jesse Cirimelli-Low
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f890160601
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add nwell routing in bca
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2023-08-21 20:12:36 -07:00 |
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Jesse Cirimelli-Low
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5a6c78865d
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singleport bitcell array laying out
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2023-08-21 19:24:06 -07:00 |
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Jesse Cirimelli-Low
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9ac894e2ef
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update bitcell array trimming
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2023-08-15 11:30:16 -07:00 |
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Sam Crow
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bb47452baf
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reapply commit c8a06a1 patch that was incorrectly reverted
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2023-08-15 11:07:04 -07:00 |
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Jesse Cirimelli-Low
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e4c15d33c4
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Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor
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2023-08-14 18:53:22 -07:00 |
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Sam Crow
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cd1b0f973d
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Revert pin/net spice object work
This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef
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2023-08-14 18:44:51 -07:00 |
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Jesse Cirimelli-Low
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0391bf6593
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add dummy mirroring for sky130 dp
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2023-08-14 14:25:57 -07:00 |
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Jesse Cirimelli-Low
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30ee5a0a2e
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add dummy cell mirroring for sky130
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2023-08-14 14:19:58 -07:00 |
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Jesse Cirimelli-Low
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74c12f944f
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mirror skywater dp
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2023-08-14 13:59:31 -07:00 |
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