af0dec7d76
Updated reset note and a doc link
2024-04-05 19:03:01 -05:00
ccc75270a8
Update getting_started.md
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I was working through using Manta for the first time, and the only bit that gave me a struggle so far was that I was expecting the `rst` signal to be active LOW. I thought this might be worth calling out in the documentation here.
Awesome project btw, will definitely be using it more and try to contribute as I can! 😄
2024-03-31 23:17:03 -05:00
5060933c72
bump node version in build_docs.yml
2024-03-14 20:58:28 -07:00
1a7adf4c63
add udev rule to docs
2024-03-14 10:28:37 -07:00
8efbad4dd8
Merge pull request #16 from fischermoseley/amaranth_rewrite
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Rewrite Manta in Amaranth HDL
2024-03-07 13:31:59 -07:00
e0aeb38cdb
update docs
2024-03-07 12:25:30 -08:00
355b5d8c76
merge origin/main into amaranth_rewrite
2024-03-07 09:59:17 -08:00
e094865528
bump pyproject version ahead of final release
2024-03-07 09:44:05 -08:00
6251c162cc
update to node 20-based checkout in CI
2024-03-07 09:35:47 -08:00
c8665e8703
update environment on CI runner
2024-03-07 09:33:50 -08:00
4ae061ffdc
add missing .gitignore
2024-03-07 09:21:40 -08:00
05f9da383c
banish all .Xil/ folders
2024-03-07 09:19:11 -08:00
04cfa41190
add logic analyzer/io core ethernet example
2024-03-07 09:18:30 -08:00
7957d41a99
fix consistency in .gitignore
2024-03-06 23:09:37 -08:00
60066ccdca
add examples for the Nexys4DDR, bump version to 1.0.0
2024-03-06 23:07:20 -08:00
05b9b450e8
add logic analyzer icestick example
2024-03-06 22:05:24 -08:00
21afbad7c4
add icestick IO core example
2024-03-06 21:47:03 -08:00
bd452d94a4
put test outputs in build/
2024-03-06 16:40:54 -08:00
6900087237
delete dead code from memory core
2024-03-06 15:08:11 -08:00
71ec1174d1
add parameterized HW tests for all memory core modes
2024-03-06 14:53:27 -08:00
0b2c286075
pull latest from main
2024-03-06 11:31:35 -08:00
d1a772784a
add environment.sh for tool paths and serial ports
2024-03-06 11:26:31 -08:00
5d5a50042f
make model tracking automatic in memory core tests
2024-03-06 01:12:36 -08:00
c1935bcb11
add random memory core tests
2024-03-05 23:59:42 -08:00
fd22c9a9f4
finish memory core test class
2024-03-05 22:44:36 -08:00
b00e4d0e60
revert wiring.Component instead of Elaboratable
2024-03-04 01:18:31 -08:00
5531277c99
even more MemoryCore tests
2024-03-04 00:43:54 -08:00
f83dc59b4e
add more MemoryCore tests
2024-03-04 00:17:36 -08:00
08adbd8ede
switch to wiring.Component instead of Elaboratable
2024-03-03 19:10:06 -08:00
be79ba28b5
define ABC for cores to inherit from
2024-03-03 18:53:08 -08:00
b729deb144
hardcode device paths in hardware tests
2024-03-03 18:31:11 -08:00
25ebae42e2
add GateMate ILA to alternatives
2024-03-03 13:57:52 -08:00
11022f474d
refactor Memory Core simulation into test class
2024-03-03 13:30:54 -08:00
e2d52a6e2d
add simulate decorator
2024-03-03 02:14:12 -08:00
2e2397013e
make mem_core_hw tests pass
2024-03-02 14:08:52 -08:00
40a57651bb
shorten methods in MemoryCore
2024-03-02 13:44:08 -08:00
6438a55192
partially revert MemoryCore updates
2024-03-02 13:31:01 -08:00
6aea5cc6e1
update MemoryCore references
2024-03-02 12:52:04 -08:00
a4d549f6f1
update static site to match README formatting
2024-02-29 15:20:11 -05:00
9a23a40d7e
update README formatting
2024-02-29 15:19:13 -05:00
74de7f2324
update README to match header
2024-02-29 15:17:56 -05:00
ab7d9105b1
add preliminary bidirectional memory core
2024-02-28 10:36:27 -08:00
8a2b9ced76
add ethernet PHY IO autoassignment
2024-02-19 17:19:23 -08:00
491db38def
tidy DHCP counter
2024-02-19 13:53:04 -08:00
ca7d743bf4
move to private methods in Manta class
2024-02-19 12:15:19 -08:00
b0dcd269bc
add from_config to memory_core
2024-02-19 11:42:28 -08:00
7ee51158d2
enforce consistent docstrings and underscores in logic analyzer core
2024-02-19 11:23:11 -08:00
e2450ddbff
complete IO core refactor
2024-02-18 15:50:51 -08:00
0c0f31be64
rewrite IO Core
2024-02-18 13:50:26 -08:00
3f724b3336
add width check function to utils
2024-02-17 21:34:17 -08:00
Kenneth Wilke
Fischer Moseley