add ethernet PHY IO autoassignment
This commit is contained in:
Fischer Moseley
parent
491db38def
commit
8a2b9ced76
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@ -22,6 +22,7 @@ class EthernetInterface(Elaboratable):
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self._fpga_ip_addr = config.get("fpga_ip_addr")
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self._host_ip_addr = config.get("host_ip_addr")
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self._udp_port = config.get("udp_port")
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self._phy = config.get("phy")
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# Convert to float first because Python considers scientific notation
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# to only represent floats, not ints.
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@ -31,14 +32,7 @@ class EthernetInterface(Elaboratable):
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self.bus_i = Signal(InternalBus())
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self.bus_o = Signal(InternalBus())
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self.rmii_clocks_ref_clk = Signal()
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self.rmii_crs_dv = Signal()
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self.rmii_mdc = Signal()
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self.rmii_mdio = Signal()
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self.rmii_rst_n = Signal()
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self.rmii_rx_data = Signal(2)
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self.rmii_tx_data = Signal(2)
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self.rmii_tx_en = Signal()
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self._phy_io = self._define_phy_io()
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self._dhcp_start = Signal()
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self._dhcp_timer = Signal(range(self._clk_freq + 1), reset=self._clk_freq)
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@ -94,22 +88,102 @@ class EthernetInterface(Elaboratable):
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Return the Amaranth signals that should be included as ports in the
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top-level Manta module.
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"""
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ports = [
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self.rmii_clocks_ref_clk,
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self.rmii_crs_dv,
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self.rmii_mdc,
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self.rmii_mdio,
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self.rmii_rst_n,
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self.rmii_rx_data,
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self.rmii_tx_data,
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self.rmii_tx_en,
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]
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return ports
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return [io[2] for io in self._phy_io]
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def _binarize_ip_addr(self, ip_addr):
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octets = [bin(int(o))[2:].zfill(8) for o in ip_addr.split(".")]
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return int("".join(octets), 2)
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def _define_phy_io(self):
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if self._phy in ["LiteEthPHYMII"]:
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return [
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("i", "mii_clocks_tx", mii_clocks_tx := Signal()),
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("i", "mii_clocks_rx", mii_clocks_rx := Signal()),
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("o", "mii_rst_n", mii_rst_n := Signal()),
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("io", "mii_mdio", mii_mdio := Signal()),
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("o", "mii_mdc", mii_mdc := Signal()),
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("i", "mii_rx_dv", mii_rx_dv := Signal()),
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("i", "mii_rx_er", mii_rx_er := Signal()),
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("i", "mii_rx_data", mii_rx_data := Signal(4)),
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("o", "mii_tx_en", mii_tx_en := Signal()),
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("o", "mii_tx_data", mii_tx_data := Signal(4)),
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("i", "mii_col", mii_col := Signal()),
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("i", "mii_crs", mii_crs := Signal()),
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]
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elif self._phy in ["LiteEthPHYRMII"]:
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return [
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("i", "rmii_clocks_ref_clk", rmii_clocks_ref_clk := Signal()),
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("o", "rmii_rst_n", rmii_rst_n := Signal()),
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("i", "rmii_rx_data", rmii_rx_data := Signal(2)),
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("i", "rmii_crs_dv", rmii_crs_dv := Signal()),
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("o", "rmii_tx_en", rmii_tx_en := Signal()),
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("o", "rmii_tx_data", rmii_tx_data := Signal(2)),
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("o", "rmii_mdc", rmii_mdc := Signal()),
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("io", "rmii_mdio", rmii_mdio := Signal()),
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]
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elif self._phy in [
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"LiteEthPHYGMII",
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"LiteEthPHYGMIIMII",
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]:
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return [
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("i", "gmii_clocks_tx", gmii_clocks_tx := Signal()),
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("o", "gmii_clocks_gtx", gmii_clocks_gtx := Signal()),
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("i", "gmii_clocks_rx", gmii_clocks_rx := Signal()),
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("o", "gmii_rst_n", gmii_rst_n := Signal()),
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("i", "gmii_int_n", gmii_int_n := Signal()),
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("io", "gmii_mdio", gmii_mdio := Signal()),
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("o", "gmii_mdc", gmii_mdc := Signal()),
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("i", "gmii_rx_dv", gmii_rx_dv := Signal()),
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("i", "gmii_rx_er", gmii_rx_er := Signal()),
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("i", "gmii_rx_data", gmii_rx_data := Signal(8)),
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("o", "gmii_tx_en", gmii_tx_en := Signal()),
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("o", "gmii_tx_er", gmii_tx_er := Signal()),
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("o", "gmii_tx_data", gmii_tx_data := Signal(8)),
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("i", "gmii_col", gmii_col := Signal()),
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("i", "gmii_crs", gmii_crs := Signal()),
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]
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elif self._phy in [
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"LiteEthS7PHYRGMII",
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"LiteEthECP5PHYRGMII",
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]:
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return [
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("o", "rgmii_clocks_tx", rgmii_clocks_tx := Signal()),
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("i", "rgmii_clocks_rx", rgmii_clocks_rx := Signal()),
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("o", "rgmii_rst_n", rgmii_rst_n := Signal()),
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("i", "rgmii_int_n", rgmii_int_n := Signal()),
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("io", "rgmii_mdio", rgmii_mdio := Signal()),
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("o", "rgmii_mdc", rgmii_mdc := Signal()),
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("i", "rgmii_rx_ctl", rgmii_rx_ctl := Signal()),
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("i", "rgmii_rx_data", rgmii_rx_data := Signal(4)),
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("o", "rgmii_tx_ctl", rgmii_tx_ctl := Signal()),
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("o", "rgmii_tx_data", rgmii_tx_data := Signal(4)),
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]
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elif self._phy in [
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"A7_1000BASEX",
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"A7_2500BASEX",
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"K7_1000BASEX",
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"K7_2500BASEX",
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"KU_1000BASEX",
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"KU_2500BASEX",
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"USP_GTH_1000BASEX",
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"USP_GTH_2500BASEX",
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"USP_GTY_1000BASEX",
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"USP_GTY_2500BASEX",
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]:
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return [
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("i", "sgmii_refclk", sgmii_refclk := Signal()),
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("i", "sgmii_rst", sgmii_rst := Signal()),
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("o", "sgmii_txp", sgmii_txp := Signal()),
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("o", "sgmii_txn", sgmii_txn := Signal()),
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("i", "sgmii_rxp", sgmii_rxp := Signal()),
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("i", "sgmii_rxn", sgmii_rxn := Signal()),
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("o", "sgmii_link_up", sgmii_link_up := Signal()),
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]
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def elaborate(self, platform):
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m = Module()
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@ -132,14 +206,7 @@ class EthernetInterface(Elaboratable):
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("i", "sys_clock", ClockSignal()),
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("i", "sys_reset", ResetSignal()),
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# PHY connection
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("i", "rmii_clocks_ref_clk", self.rmii_clocks_ref_clk),
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("i", "rmii_crs_dv", self.rmii_crs_dv),
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("o", "rmii_mdc", self.rmii_mdc),
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("io", "rmii_mdio", self.rmii_mdio),
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("o", "rmii_rst_n", self.rmii_rst_n),
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("i", "rmii_rx_data", self.rmii_rx_data),
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("o", "rmii_tx_data", self.rmii_tx_data),
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("o", "rmii_tx_en", self.rmii_tx_en),
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*self._phy_io,
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# DHCP
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# ("o", "dhcp_done", 1),
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# ("o", "dhcp_ip_address", 1),
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@ -265,15 +332,17 @@ class EthernetInterface(Elaboratable):
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"""
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liteeth_config = self._config.copy()
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# Randomly assign a MAC address if one is not specified in the configuration.
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# This will choose a MAC address in the Locally Administered, Administratively Assigned group.
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# For more information, see:
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# Randomly assign a MAC address if one is not specified in the
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# configuration. This will choose a MAC address in the Locally
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# Administered, Administratively Assigned group. For more information,
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# please reference:
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# https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses
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if "mac_address" not in liteeth_config:
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addr = list(f"{randint(0, (2**48) - 1):012x}")
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addr[1] = "2"
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liteeth_config["mac_address"] = int("".join(addr), 16)
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print(liteeth_config["mac_address"])
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# Force use of DHCP
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liteeth_config["dhcp"] = True
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