Update getting_started.md

I was working through using Manta for the first time, and the only bit that gave me a struggle so far was that I was expecting the `rst` signal to be active LOW.  I thought this might be worth calling out in the documentation here.

Awesome project btw, will definitely be using it more and try to contribute as I can! 😄

doc/getting_started.md

@@ -60,6 +60,8 @@ This Manta instance has an IO Core and a Logic Analyzer, each containing a numbe
 
 Lastly, we Manta can automatically generate a copy-pasteable Verilog snippet to instantiate Manta in your design by running `manta inst [config_file]`. For example, the following snippet is generated for the configuration above:
 
+> Note: The reset signal, `rst`, is an active HIGH signal.
+
 ```verilog
 manta manta_inst (
     .clk(clk),
@@ -73,4 +75,4 @@ manta manta_inst (
     .larry(larry),
     .curly(curly),
     .moe(moe));
-```
+```