Fischer Moseley
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18fcbfe1f2
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add IO core example
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2023-03-23 23:15:55 -04:00 |
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Fischer Moseley
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c4b6358537
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clean up port autodetection
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2023-03-23 22:27:51 -04:00 |
Fischer Moseley
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a562c8136c
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add ability to autodetect serial port
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2023-03-23 20:46:49 -04:00 |
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Fischer Moseley
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f7077f96d8
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add lut ram operations to Python API
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2023-03-23 19:38:19 -04:00 |
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Fischer Moseley
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c85cc4d357
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tweak lut_ram example
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2023-03-23 18:24:29 -04:00 |
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Fischer Moseley
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a57b5908f2
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add verbose output to serial
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2023-03-23 18:10:52 -04:00 |
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Fischer Moseley
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53c116a4f0
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add global address assignment
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2023-03-19 11:17:39 -06:00 |
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Fischer Moseley
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500267798f
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add example instantiation to top of autogenerated output
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2023-03-19 10:57:32 -06:00 |
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Fischer Moseley
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edd50168e2
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refactor IO core read/write to be less ugly
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2023-03-17 20:12:57 -04:00 |
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Fischer Moseley
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3cf5164d23
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add bus read/write to python
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2023-03-17 19:04:59 -04:00 |
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Fischer Moseley
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f2a0ede9f4
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update docs a lil
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2023-03-16 12:58:40 -04:00 |
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Fischer Moseley
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dcffb55710
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update docs and readme
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2023-03-16 12:49:21 -04:00 |
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Fischer Moseley
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d46e833529
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can now successfully autogenerate and build io cores
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2023-03-16 12:13:46 -04:00 |
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Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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bdc082e8d6
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add io core, playing with verilator lint
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2023-03-16 08:30:19 -04:00 |
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Fischer Moseley
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11495fca61
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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Fischer Moseley
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fade794333
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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Fischer Moseley
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4540aebf6d
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add some fixes for macos serial prots
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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aa2ba43e8f
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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8630da53d8
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hack manta source files together
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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2c9168c721
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add a little info on the io cores
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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dfad0ad7c1
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one more docs update
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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28aa6461c2
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update lotsa docs
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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05e79ee466
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move accent color definition
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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62910c5b4f
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update docs
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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f193f51660
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fix docs_dir in mkdocs.yml
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a57848f6df
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add docs_dir to mkdocs.yml
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d6df33921
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add site config to mkdocs
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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8cce0c0eca
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update file extension on github actions
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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7bb53d616b
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build docs
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a6e7aa287d
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add top-level interface ports to top-level declaration
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a5518c1873
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add core chain module self-wiring
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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f536488550
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add top level ports procedurally
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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3fda03ec90
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break up hdl definition into multiple member functinos
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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9dba38925b
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add module definitions to generated hdl
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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7d98988b87
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add autogenerated instantiations and connections for LA cores
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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8c645a5115
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update github workflows to use Makefile for sim
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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f5f7f91bdc
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fix LogicAnalyzerCore instantiation from file
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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ca2579e471
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banish .DS_Store
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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334aa8c005
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refactor __init__.py to be object-oriented
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5e2f02ebd6
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d9792702a
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e022696b31
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add working example for macOS bug
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a70ba2d0a8
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replace uart modules with zipcpu for testing, TX seems to misalign itself
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70e2bd10e7
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rename, slightly patch bridge_tx
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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3124430064
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tidy up a little, convert things to verilog
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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3ff4298e24
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works (kinda) on hardware
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70154f6904
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add uart_rx module, bus seems to be working end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5454ed37e9
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add bus_tb, has nearly all of manta end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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c1620871cf
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add lut memory and tests, still need to sort out pipelining
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2023-03-14 16:24:56 -04:00 |