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tidy up a little, convert things to verilog

This commit is contained in:
Fischer Moseley 2023-03-02 22:57:46 -05:00
parent 3ff4298e24
commit 3124430064
8 changed files with 99 additions and 177 deletions
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49
examples/nexys_a7/counter/src/bto7s.sv
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@ -1,49 +0,0 @@
module bto7s(
input wire [3:0] x_in,
output logic [6:0] s_out);
logic sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
logic [15:0] num;
assign num[0] = ~x_in[3] && ~x_in[2] && ~x_in[1] && ~x_in[0];
assign num[1] = ~x_in[3] && ~x_in[2] && ~x_in[1] && x_in[0];
assign num[2] = x_in == 4'd2;
assign num[3] = x_in == 4'd3;
assign num[4] = x_in == 4'd4;
assign num[5] = x_in == 4'd5;
assign num[6] = x_in == 4'd6;
assign num[7] = x_in == 4'd7;
assign num[8] = x_in == 4'd8;
assign num[9] = x_in == 4'd9;
assign num[10] = x_in == 4'd10;
assign num[11] = x_in == 4'd11;
assign num[12] = x_in == 4'd12;
assign num[13] = x_in == 4'd13;
assign num[14] = x_in == 4'd14;
assign num[15] = x_in == 4'd15;
/* you could also do this with generation, like this:
*
* genvar i;
* generate
* for (i=0; i<16; i=i+1)begin
* assign num[i] = (x_in == i);
* end
* endgenerate
*/
/* assign the seven output segments, sa through sg, using a "sum of products"
* approach and the diagram above.
*/
assign sa = num[0] || num[2] || num[3] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[12] ||num[14] ||num[15];
assign sb = num[0] || num[1] || num[2] || num[3] || num[4] || num[7] || num[8] || num[9] || num[10] || num[13];
assign sc = num[0] || num[1] || num[3] || num[4] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[11] || num[13];
assign sd = num[0] || num[2] || num[3] || num[5] || num[6] || num[8] || num[9] || num[11] || num[12] || num[13] || num[14];
assign se = num[0] || num[2] || num[6] || num[8] || num[10] || num[11] || num[12] || num[13] || num[14] || num[15];
assign sf = num[0] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[12] || num[14] || num[15];
assign sg = num[2] || num[3] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[13] || num[14] ||num[15];
endmodule

24
examples/nexys_a7/counter/src/manta.sv → examples/nexys_a7/counter/src/manta.v
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@ -20,7 +20,7 @@ module manta(
// .axiod(urx_brx_axid),
// .axiov(urx_brx_axiv));
rxuart urx(
.i_clk(clk),
.i_uart_rx(rxd),
@ -28,8 +28,8 @@ module manta(
.o_data(urx_brx_axid));
// uart_rx --> bridge_rx signals
logic [7:0] urx_brx_axid;
logic urx_brx_axiv;
reg [7:0] urx_brx_axid;
reg urx_brx_axiv;
bridge_rx brx (
.clk(clk),
@ -43,10 +43,10 @@ module manta(
.req_ready(1'b1));
// bridge_rx --> mem_1 signals
logic [15:0] brx_mem_1_addr;
logic [15:0] brx_mem_1_wdata;
logic brx_mem_1_rw;
logic brx_mem_1_valid;
reg [15:0] brx_mem_1_addr;
reg [15:0] brx_mem_1_wdata;
reg brx_mem_1_rw;
reg brx_mem_1_valid;
lut_mem #(
.DEPTH(8),
@ -65,8 +65,8 @@ module manta(
.rw_o(),
.valid_o(mem_1_btx_valid));
logic [15:0] mem_1_btx_rdata;
logic mem_1_btx_valid;
reg [15:0] mem_1_btx_rdata;
reg mem_1_btx_valid;
bridge_tx btx (
.clk(clk),
@ -80,9 +80,9 @@ module manta(
.axior(btx_utx_axir));
// bridge_tx --> uart_tx signals
logic [7:0] btx_utx_axid;
logic btx_utx_axiv;
logic btx_utx_axir;
reg [7:0] btx_utx_axid;
reg btx_utx_axiv;
reg btx_utx_axir;
uart_tx #(
.DATA_WIDTH(8),

0
examples/nexys_a7/counter/src/rxuart.v → examples/nexys_a7/counter/src/rx_uart.v
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45
examples/nexys_a7/counter/src/seven_segment_controller.sv
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@ -1,45 +0,0 @@
module seven_segment_controller #(parameter COUNT_TO = 100000)
( input wire clk_in,
input wire rst_in,
input wire [31:0] val_in,
output logic[6:0] cat_out,
output logic[7:0] an_out
);
logic[7:0] segment_state;
logic[31:0] segment_counter;
logic [3:0] routed_vals;
logic [6:0] led_out;
bto7s mbto7s (.x_in(routed_vals), .s_out(led_out));
assign cat_out = ~led_out;
assign an_out = ~segment_state;
always_comb begin
case(segment_state)
8'b0000_0001: routed_vals = val_in[3:0];
8'b0000_0010: routed_vals = val_in[7:4];
8'b0000_0100: routed_vals = val_in[11:8];
8'b0000_1000: routed_vals = val_in[15:12];
8'b0001_0000: routed_vals = val_in[19:16];
8'b0010_0000: routed_vals = val_in[23:20];
8'b0100_0000: routed_vals = val_in[27:24];
8'b1000_0000: routed_vals = val_in[31:28];
default: routed_vals = val_in[3:0];
endcase
end
always_ff @(posedge clk_in)begin
if (rst_in)begin
segment_state <= 8'b0000_0001;
segment_counter <= 32'b0;
end else begin
if (segment_counter == COUNT_TO)begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0],segment_state[7]};
end else begin
segment_counter <= segment_counter +1;
end
end
end
endmodule //seven_segment_controller

85
examples/nexys_a7/counter/src/ssd.v Normal file
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@ -0,0 +1,85 @@
module ssd(
input wire clk_in,
input wire rst_in,
input wire [31:0] val_in,
output reg[6:0] cat_out,
output reg[7:0] an_out);
parameter COUNT_TO = 100000;
logic[7:0] segment_state;
logic[31:0] segment_counter;
logic [3:0] routed_vals;
logic [6:0] led_out;
bto7s mbto7s (.x_in(routed_vals), .s_out(led_out));
assign cat_out = ~led_out;
assign an_out = ~segment_state;
always @(*) begin
case(segment_state)
8'b0000_0001: routed_vals = val_in[3:0];
8'b0000_0010: routed_vals = val_in[7:4];
8'b0000_0100: routed_vals = val_in[11:8];
8'b0000_1000: routed_vals = val_in[15:12];
8'b0001_0000: routed_vals = val_in[19:16];
8'b0010_0000: routed_vals = val_in[23:20];
8'b0100_0000: routed_vals = val_in[27:24];
8'b1000_0000: routed_vals = val_in[31:28];
default: routed_vals = val_in[3:0];
endcase
end
always @(posedge clk_in) begin
if (rst_in) begin
segment_state <= 8'b0000_0001;
segment_counter <= 32'b0;
end
else begin
if (segment_counter == COUNT_TO) begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0],segment_state[7]};
end else begin
segment_counter <= segment_counter +1;
end
end
end
endmodule
module bto7s(
input wire [3:0] x_in,
output reg [6:0] s_out);
reg sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
reg [15:0] num;
assign num[0] = ~x_in[3] && ~x_in[2] && ~x_in[1] && ~x_in[0];
assign num[1] = ~x_in[3] && ~x_in[2] && ~x_in[1] && x_in[0];
assign num[2] = x_in == 4'd2;
assign num[3] = x_in == 4'd3;
assign num[4] = x_in == 4'd4;
assign num[5] = x_in == 4'd5;
assign num[6] = x_in == 4'd6;
assign num[7] = x_in == 4'd7;
assign num[8] = x_in == 4'd8;
assign num[9] = x_in == 4'd9;
assign num[10] = x_in == 4'd10;
assign num[11] = x_in == 4'd11;
assign num[12] = x_in == 4'd12;
assign num[13] = x_in == 4'd13;
assign num[14] = x_in == 4'd14;
assign num[15] = x_in == 4'd15;
assign sa = num[0] || num[2] || num[3] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[12] ||num[14] ||num[15];
assign sb = num[0] || num[1] || num[2] || num[3] || num[4] || num[7] || num[8] || num[9] || num[10] || num[13];
assign sc = num[0] || num[1] || num[3] || num[4] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[11] || num[13];
assign sd = num[0] || num[2] || num[3] || num[5] || num[6] || num[8] || num[9] || num[11] || num[12] || num[13] || num[14];
assign se = num[0] || num[2] || num[6] || num[8] || num[10] || num[11] || num[12] || num[13] || num[14] || num[15];
assign sf = num[0] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[12] || num[14] || num[15];
assign sg = num[2] || num[3] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[13] || num[14] ||num[15];
endmodule

2
examples/nexys_a7/counter/src/top_level.sv
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@ -28,7 +28,7 @@ module top_level (
logic [6:0] cat;
assign {cg,cf,ce,cd,cc,cb,ca} = cat;
seven_segment_controller ss (
ssd ssd (
.clk_in(clk),
.rst_in(btnc),
.val_in( (manta.mem_1_btx_rdata << 16) | (manta.brx_mem_1_wdata) ),

69
examples/nexys_a7/counter/src/uart_rx.v
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@ -1,69 +0,0 @@
`default_nettype none
`timescale 1ns / 1ps
module uart_rx(
input wire clk,
input wire rst,
input wire rxd,
output reg [DATA_WIDTH - 1:0] axiod,
output reg axiov
);
parameter DATA_WIDTH = 0;
parameter CLK_FREQ_HZ = 0;
parameter BAUDRATE = 0;
localparam BAUD_PERIOD = CLK_FREQ_HZ / BAUDRATE;
reg [$clog2(BAUD_PERIOD) - 1:0] baud_counter;
reg [$clog2(DATA_WIDTH + 2):0] bit_index;
reg [DATA_WIDTH + 2 : 0] data_buf;
reg prev_rxd;
reg busy;
always_ff @(posedge clk) begin
prev_rxd <= rxd;
axiov <= 0;
baud_counter <= (baud_counter == BAUD_PERIOD - 1) ? 0 : baud_counter + 1;
// reset logic
if(rst) begin
bit_index <= 0;
axiod <= 0;
busy <= 0;
baud_counter <= 0;
end
// start receiving if we see a falling edge, and not already busy
else if (prev_rxd && ~rxd && ~busy) begin
busy <= 1;
data_buf <= 0;
baud_counter <= 0;
end
// if we're actually receiving
else if (busy) begin
if (baud_counter == BAUD_PERIOD / 2) begin
data_buf[bit_index] <= rxd;
bit_index <= bit_index + 1;
if (bit_index == DATA_WIDTH + 1) begin
busy <= 0;
bit_index <= 0;
if (rxd && ~data_buf[0]) begin
axiod <= data_buf[DATA_WIDTH : 1];
axiov <= 1;
end
end
end
end
end
endmodule
`default_nettype wire

2
examples/nexys_a7/counter/write.py
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@ -4,7 +4,7 @@ from time import sleep
with serial.Serial("/dev/tty.usbserial-210292AE39A41", 115200) as ser:
for i in range(8):
req = '{:04X}'.format(i)
req = f"M{req}0000\r\n "
req = f"M{req}1234\r\n "
req = req.encode('ascii')
ser.write(req)