c116808fdb
Remove duplicated code
2008-07-17 11:46:36 +01:00
642fbe9fc5
Correct check for arrays
2008-07-17 11:31:06 +01:00
f3753ea9ad
Add warning that arrays are not yet implemented
2008-07-15 18:09:18 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
f84f50842c
Support bufif for tri1 nets
2008-07-14 19:13:11 +01:00
65720f49fe
Simple bufif cases
2008-07-14 19:00:58 +01:00
6243736481
Pull-up/pull-down logic devices
2008-07-14 12:04:20 +01:00
e331e4831b
Fix nexus_to_expr where nexus has IVL_LPM_SELECT_PV
2008-07-14 11:53:38 +01:00
78ee61558d
Remove redundant test
...
Signal is guaranteed to appear in arch_scope or its parent
by the surrounding `if' statement.
2008-07-13 15:27:07 +01:00
07c4ff7ea7
Add assertion about result of lpm_to_expr
2008-07-13 15:26:03 +01:00
e5422dddd2
Remove useless `ignore' param to nexus_to_expr
2008-07-13 15:24:35 +01:00
6af201ea03
Refactor nexus expansion functions.
...
Now a single function nexus_to_expr
2008-07-13 15:17:14 +01:00
27a40cfdcd
Constant assignments to outputs
...
If the Verilog source contained a continuous assignment
of a constant to an output, it would not be present in
the VHDL output. This patch generates a VHDL continous
assignment in these cases.
2008-07-13 13:02:17 +01:00
3bd480a375
Allow ouput to be read if connected to child output
...
If output P of A is connected to output Q of B (and A is
instantiated inside B) then VHDL does not allow B to read
the value of Q (also P), but Verilog does. To get around
this the output Q is mapped to P_Sig which is then connected
to P, this allows B to read the value of P/Q via P_Sig.
2008-07-13 12:41:02 +01:00
bd5cc96956
Correct vector sizes for bit select
2008-07-08 00:20:31 +01:00
860a74ddd8
Allow LPMs in port maps
2008-07-07 20:41:29 +01:00
47db80315c
Add sign extension LPM
2008-07-07 19:27:52 +01:00
37fe6e4219
Dummy implementation of IVL_LO_BUF*
2008-07-07 15:49:51 +01:00
4db5b9d7ed
Add unary OR/NOR
...
These are currently implemented with reference to an external
Reduce_OR function
2008-07-07 15:23:57 +01:00
dadd145d09
Add message for unsupported LPM nexus pointer
2008-07-07 15:04:28 +01:00
c33600bcc3
Add concatenation operator
2008-07-06 18:21:34 +01:00
3d0a2b55ce
Avoid declaring same function multiple times
...
If it appears in multiple places in the hierarchy
2008-07-04 12:03:37 +01:00
dbbadbc309
Make sure the renamed signal is used in the sensitivity list
2008-07-03 16:13:02 +01:00
fb08164cbc
List some more illegal VHDL names
2008-07-03 15:20:43 +01:00
7e999c5496
Fix continuous assignment of constants
...
E.g. in assign p = 1 the RHS signal in the generated LPM now
has a correct intial value (and it will never be written to
elsewhere)
2008-07-03 15:13:12 +01:00
35c66744db
Cleanup and remove debug output
2008-07-01 11:31:00 +01:00
930e04f6c7
Ensure port map expressions are globally static
2008-07-01 11:28:02 +01:00
37756b8d06
Avoid mapping a signal to itself
2008-07-01 11:13:02 +01:00
596c93ce7e
Rename instance if it has the same name as the type
2008-07-01 11:05:24 +01:00
624943b3ca
Simplify port map generation code
2008-07-01 10:59:31 +01:00
ef89a760d6
Add vhdl_element::print method for debugging
2008-07-01 10:44:20 +01:00
f03dfb50ad
Refactor nexus_to_var_ref
2008-07-01 10:33:46 +01:00
4e73b1b133
Fix bug when resolving nexus to VHDL signal
2008-06-30 17:47:45 +01:00
b82ca28190
Add XOR logic type and fix part select
2008-06-30 16:18:55 +01:00
f800298d01
Fix memory leak
2008-06-27 12:29:50 +01:00
301a25303f
Remove useless assertion
2008-06-27 12:21:53 +01:00
b24eb6ce88
Handle local variables in functions
2008-06-27 12:21:27 +01:00
fd60bfd3d2
Rewrite function parameter finding code
2008-06-27 12:18:39 +01:00
500442e5c5
Working function calls
2008-06-25 22:15:57 +01:00
d997397c38
Generate function calls with parameters
2008-06-25 21:49:22 +01:00
7773000c36
Generate function declarations
2008-06-25 21:40:35 +01:00
042f7ccbcd
Generate a return type for functions
2008-06-25 18:43:50 +01:00
44aa8a6b91
Associate signals with scopes rather than entities
2008-06-25 18:12:57 +01:00
43c671cb5c
Emit VHDL for function declarations
2008-06-25 18:00:48 +01:00
c01c2bd742
Dummy code for handling function scopes
2008-06-25 12:48:46 +01:00
e77bb0157e
Remove redundant methods from vhdl_arch
2008-06-24 19:39:05 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
449cd0a76e
Correctly generate signed/unsigned types
2008-06-23 14:28:27 +01:00
e5ef0d97bd
Fix signed/unsigned resizing
2008-06-23 13:04:28 +01:00
08d80b35cb
Rename signals that would be illegal VHDL names
2008-06-19 16:15:47 +01:00
561953e494
Minial LPM to support continuous assignments
2008-06-16 19:41:01 +01:00
83a7796b74
Make sure signal names conform to VHDL rules
2008-06-16 17:37:17 +01:00
2fb57805ea
Use signed rather than std_logic_vector
...
Arithmetic operators now working correctly
2008-06-14 18:03:25 +01:00
005df31a0d
Use renamed signal in expressions, if there is one
2008-06-13 12:39:18 +01:00
d6193c1622
Add _Reg internal signal if output is registered
2008-06-13 12:34:27 +01:00
26a2c69c2e
Change architecture name to `FromVerilog'
2008-06-11 11:31:43 +01:00
babe694366
Generate port mappings
2008-06-10 13:58:41 +01:00
7560b29fb9
Find signals to map together
2008-06-10 12:21:48 +01:00
3106fe0ed6
Generate port declarations for entities.
...
But doesn't emit them yet!
2008-06-09 16:27:04 +01:00
e29954e03f
Generate concurrent assignments from logic gates
2008-06-09 15:05:32 +01:00
3b5d56e087
Allow n-ary expressions
2008-06-09 14:53:50 +01:00
aa91186119
Add AST elements for unary/binary expressions to model logic gates
2008-06-09 14:39:58 +01:00
d08f5af9c6
Add concurrent assignments
2008-06-09 14:21:55 +01:00
b96e471fa2
Stub code for handling logic gates
2008-06-09 14:08:27 +01:00
110a1b2ac7
Replace type classes with enumeration
2008-06-08 12:48:56 +01:00
fbf85398da
Support converting bit strings to std_logic
2008-06-07 16:19:10 +01:00
8c3461f0ff
Generate sensitivity lists properly and add signal declarations
2008-06-07 11:48:38 +01:00
c3ac1aac8c
Remove debugging messages from output
2008-06-04 21:07:50 +01:00
7bd1565cfb
$display now (mostly) working
2008-06-04 20:42:44 +01:00
ab6ae621cb
Remove useless comments in output
2008-06-02 20:24:25 +01:00
17ae0a6a09
Fix a bug where the same instantiation appeared multiple times
2008-06-02 18:05:39 +01:00
041925c123
Component instantiation to replicate Verilog hierarchy
2008-06-02 17:45:58 +01:00
9292a087e8
Generate VHDL processes from Verilog processes
2008-06-02 16:17:01 +01:00
7c9d154461
Forgot source files for entity generation
2008-05-31 15:31:48 +01:00
Nick Gasson