Commit Graph

124 Commits

Author SHA1 Message Date
Nick Gasson 712e08ebe8 Emit useful error message for pr2362211
This prints out an error message rather than crashing out with
an assertion failure when a function assigns to a non-local
variable, which cannot be done in VHDL.
2008-12-07 16:50:07 -08:00
Nick Gasson c06c49c992 Fix assignment of constant to input
If a module's input was connected to a nexus that contained
a constant driver. That constant would be incorrectly generated
as an assignment to the input *inside* the child module (instead
of an assignment inside the instantiating module).
2008-12-07 16:45:05 -08:00
Nick Gasson 1cc5586c4d Add debugging output to VHDL target
Prints progress when -pdebug=1 specified.

Adds a new debug_msg function to print progress messages.
2008-11-29 20:16:09 -08:00
Cary R cedbdb63fa VHDL make comment for temporaries unique.
Make the comment for local signals (temporaries) unique from
normal signals.
2008-11-18 20:28:28 -08:00
Nick Gasson 7529034c7a Fix incorrect temporary size with padding
Fix for pr2224949

The compiler generates a concatenation LPM to zero-pad ports when the
signal widths don't match up. However, when the VHDL generator generated
the input signals to this LPM it incorrectly sized them to be the width
of the result.
2008-11-18 15:00:00 -08:00
Nick Gasson 256454960c Add complete list of VHDL reserved words
make_safe_name now makes sure a VHDL signal is never given a
name that conflicts with any reserved words. If it does, we
just prepend VL_.

(This code was already present, but the full list of reserved
words wasn't.)
2008-11-13 15:45:41 -08:00
Nick Gasson 5fd32937f2 Fix overly restrictive check for slices
Fixes some instances of "can only select from a variable reference"
2008-11-12 22:26:44 +00:00
Larry Doolittle 9b640f3114 Shadow reduction part 4
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  This patch set covers the tgt-vhdl
directory, and was tested by Nick.
2008-10-30 21:46:44 -07:00
Nick Gasson 6fe7583784 Cary R.'s additional system functions, real value error messages, etc.
I've changed the find_entity() error messages to asserts since
this should be fixed by the previous patch.
2008-09-06 12:06:01 +01:00
Nick Gasson a34348bb35 Add (temporary) error for ICT_SCOPE_GENERATE
Generate scopes were previously ignored, and this would cause a segfault
later on. This patch gives an error whenever it encounters a generate
scope. This should be removed once generate statements are implemented.
2008-09-06 11:38:37 +01:00
Nick Gasson 63a1e25129 Catch case where component name and instance differ only in case
This causes an error in VHDL (which is case-insensitive). This 
patch simply appends _Inst to the instance name if it detects this.
2008-08-22 20:20:17 +01:00
Nick Gasson 535ef6be38 Change function return value from Verilog_Result to <funcname>_Result 2008-08-21 19:44:12 +01:00
Nick Gasson c404b761b7 Change `out' ports to `buffer' when the signal is read
Previously this was handled by creating an internal
signal that was connected to the output and could also
be read inside the entity. The correct solution is to
make the output `buffer' rather than `out'. However, this
does not work in the case when an output is connected to
an output of a child entity, and that values is read
in the parent. In this case *both* the outputs of the child
and the parent need to be made `buffer'.
2008-08-11 20:48:28 +01:00
Nick Gasson 7ed8c0915d Add file/line comments to signal declarations 2008-08-08 20:28:16 +01:00
Nick Gasson 090ae5fa56 Catch case where signal with same name in task and module
This fixes task3.14C
2008-08-08 19:47:20 +01:00
Nick Gasson 13cb81f4bb Add task signals to containing architecture
This is necessary to support the in-line expansion of tasks
2008-08-08 19:31:45 +01:00
Nick Gasson bb0efda526 Make make_safe_name case insensitive 2008-08-07 17:58:42 +01:00
Nick Gasson 49a2693357 Add file / line number information to functions 2008-08-03 14:46:57 +01:00
Nick Gasson 10a5ca199d Add file / line number comments to instantiations 2008-08-03 14:38:08 +01:00
Nick Gasson c2f622327f Use ivl_scope_def_* for definition file/line numbers 2008-08-03 14:34:41 +01:00
Nick Gasson 45dfa28dba Remember signal pin a nexus was attached to
Also modify nexus_to_var_ref to set the correct array
offset when the signal is an array (the offset comes
from the pin).
2008-08-03 11:41:26 +01:00
Nick Gasson c8cbac58f5 Add forward declarations for functions
This patch adds a forward declaration for every user funciton.
This fixes VHDL compile problems if a function calls another
before it has been declared.
2008-08-03 10:50:31 +01:00
Nick Gasson 5d0df8d880 Change format of line file/line numbers 2008-08-02 10:42:00 +01:00
Nick Gasson bb80b432e6 Add comments file/line number comments
Added to entities, architectures, and processes
2008-08-01 21:21:42 +01:00
Nick Gasson baa2363e85 Split logic device code into separate file 2008-07-30 10:13:08 +01:00
Nick Gasson e5b8abfb23 Remove debugging output 2008-07-29 21:15:51 +01:00
Nick Gasson 9a5b7bb0b0 Connect signals together if joined in a nexus 2008-07-29 21:03:00 +01:00
Nick Gasson eaf1cc9120 Fix assertion failure with arrayed signals 2008-07-29 19:47:17 +01:00
Nick Gasson 3bcd42dc8f Fix case where logic device has no valid output 2008-07-29 19:39:20 +01:00
Nick Gasson 744fbed783 Finish re-writing nexus code 2008-07-29 19:33:40 +01:00
Nick Gasson c9454b346e Fix module3.12B 2008-07-29 19:04:41 +01:00
Nick Gasson 5ec2c37e7e Get functions working again 2008-07-29 15:29:49 +01:00
Nick Gasson 25602e487d Comment 2008-07-29 15:12:51 +01:00
Nick Gasson e037ffd952 Create temporaries for LPM outputs 2008-07-29 15:09:58 +01:00
Nick Gasson 48c1a7982c Make seen_nexus private 2008-07-29 14:24:04 +01:00
Nick Gasson a842b327c7 Generate constant drivers as concurrent assignments 2008-07-29 14:02:05 +01:00
Nick Gasson f8034d69ef Fix constants in nexuses 2008-07-29 13:30:54 +01:00
Nick Gasson 680c6f0503 Make sure LPMs have valid inputs/outputs 2008-07-29 13:06:21 +01:00
Nick Gasson 39717989a8 Call set_active_entity in the right places 2008-07-29 13:04:29 +01:00
Nick Gasson c26b7ce675 Port maps 2008-07-29 13:02:55 +01:00
Nick Gasson c6f6ea7358 Instantiation working again 2008-07-29 12:21:19 +01:00
Nick Gasson c0c838f1bc Logic devices now working again 2008-07-29 12:11:44 +01:00
Nick Gasson 1a45e9164f Find signal a logic device is connected to 2008-07-29 12:04:40 +01:00
Nick Gasson 8a5f129e56 Draw nexus in multiple passes 2008-07-29 12:00:26 +01:00
Nick Gasson 65c2ceb89d Build entity hierarchy in separate stages 2008-07-29 11:01:02 +01:00
Nick Gasson e4c2400eb2 Refactor the expression->time code into a single function 2008-07-23 16:18:49 +01:00
Nick Gasson 30fdadc525 Support delays in logic devices 2008-07-23 13:40:42 +01:00
Nick Gasson 2d79e1a2e0 Store the currently active entity 2008-07-19 14:45:00 +01:00
Nick Gasson 4d9f029000 Generate correct array bounds 2008-07-17 14:38:07 +01:00
Nick Gasson 1d3ac6bc1f Generate VHDL array type declarations of Verilog arrays 2008-07-17 13:08:55 +01:00