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iverilog/parse.y

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Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
%{
/*
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
* Copyright (c) 1998-2012 Stephen Williams (steve@icarus.com)
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
Create a config.h.in file to hold all the config junk, and support gcc 3.0. (Stephan Boettcher)
2001-07-25 05:10:48 +02:00
# include "config.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include "parse_misc.h"
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
# include "compiler.h"
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
# include "pform.h"
Fixes for stubborn compilers.
2005-12-05 22:21:18 +01:00
# include "Statement.h"
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
# include "PSpec.h"
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
# include <stack>
header includes for gcc-4.3 compatibility minimal changes required to build without error tested with gcc-4.3 (Debian 4.3-20071130-1) 4.3.0 20071130 (experimental)
2008-01-05 00:23:47 +01:00
# include <cstring>
Fix handling of inline decloration without wire keyword.
2003-02-08 00:16:09 +01:00
# include <sstream>
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
class PSpecPath;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
extern void lex_start_table();
extern void lex_end_table();
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
bool have_timeunit_decl = false;
bool have_timeprec_decl = false;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
static list<PExpr*>* param_active_range = 0;
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
static bool param_active_signed = false;
static ivl_variable_type_t param_active_type = IVL_VT_LOGIC;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
/* Port declaration lists use this structure for context. */
static struct {
NetNet::Type port_net_type;
NetNet::PortType port_type;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
ivl_variable_type_t var_type;
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
bool sign_flag;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>* range;
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
data_type_t* data_type;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
} port_declaration_context = {NetNet::NONE, NetNet::NOT_A_PORT,
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
IVL_VT_NO_TYPE, false, 0, 0};
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
/* The task and function rules need to briefly hold the pointer to the
task/function that is currently in progress. */
static PTask* current_task = 0;
static PFunction* current_function = 0;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
static stack<PBlock*> current_block_stack;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
Add a waring that timing check delayed signals will not be driven. The $setuphold and $recrem timing checks can create delayed signals that are needed to get a model to work correctly when negative timing check values are used. Since we do not support timing checks and just ignore them this can create simulation problems when a user tries to use these delayed signals since they are not driven. This patch adds a waring when the circuit is being compiled that these delayed signals will not be driven. This will be needed until we get time to add the real timing checks are mimic the delayed properties of the timing check.
2009-10-31 03:16:42 +01:00
/* This is used to keep track of the extra arguments after the notifier
* in the $setuphold and $recrem timing checks. This allows us to print
* a warning message that the delayed signals will not be created. We
* need to do this since not driving these signals creates real
* simulation issues. */
static unsigned args_after_notifier;
Account for bison 1.35 and stack manipulations.
2002-12-10 06:49:51 +01:00
/* Later version of bison (including 1.35) will not compile in stack
extension if the output is compiled with C++ and either the YYSTYPE
or YYLTYPE are provided by the source code. However, I can get the
old behavior back by defining these symbols. */
# define YYSTYPE_IS_TRIVIAL 1
# define YYLTYPE_IS_TRIVIAL 1
Set proper line text for later bison.
2003-01-17 06:48:02 +01:00
/* Recent version of bison expect that the user supply a
YYLLOC_DEFAULT macro that makes up a yylloc value from existing
values. I need to supply an explicit version to account for the
text field, that otherwise won't be copied. */
Get value for vpoiConstType correct.
2004-01-13 03:55:50 +01:00
# define YYLLOC_DEFAULT(Current, Rhs, N) do { \
(Current).first_line = (Rhs)[1].first_line; \
(Current).first_column = (Rhs)[1].first_column; \
(Current).last_line = (Rhs)[N].last_line; \
(Current).last_column = (Rhs)[N].last_column; \
(Current).text = (Rhs)[1].text; } while (0)
Set proper line text for later bison.
2003-01-17 06:48:02 +01:00
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/*
Drive strengths for continuous assignments.
2002-01-12 05:03:39 +01:00
* These are some common strength pairs that are used as defaults when
* the user is not otherwise specific.
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
*/
OpenBSD wants static before const This is not really a problem, but to keep OpenBSD quiet we put static before const (-W warning).
2010-11-02 22:38:25 +01:00
static const struct str_pair_t pull_strength = { IVL_DR_PULL, IVL_DR_PULL };
static const struct str_pair_t str_strength = { IVL_DR_STRONG, IVL_DR_STRONG };
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
static list<pair<perm_string,PExpr*> >* make_port_list(char*id, PExpr*expr)
{
list<pair<perm_string,PExpr*> >*tmp = new list<pair<perm_string,PExpr*> >;
tmp->push_back(make_pair(lex_strings.make(id), expr));
delete[]id;
return tmp;
}
static list<pair<perm_string,PExpr*> >* make_port_list(list<pair<perm_string,
PExpr*> >*tmp,
char*id, PExpr*expr)
{
tmp->push_back(make_pair(lex_strings.make(id), expr));
delete[]id;
return tmp;
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
list<PExpr*>* make_range_from_width(uint64_t wid)
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
{
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*range = new list<PExpr*>;
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
range->push_back(new PENumber(new verinum(wid-1, integer_width)));
range->push_back(new PENumber(new verinum((uint64_t)0, integer_width)));
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
return range;
}
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
/*
An enumeration cannot have duplicate values. Add code to check that an enumeration does not have duplicate values.
2011-09-30 04:34:23 +02:00
* Make a range vector from an existing pair of expressions.
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
*/
static vector<PExpr*>* make_range_vector(list<PExpr*>*that)
{
assert(that->size() == 2);
vector<PExpr*>*tmp = new vector<PExpr*> (2);
tmp->at(0) = that->front();
tmp->at(1) = that->back();
delete that;
return tmp;
}
/*
* Make a range vector from a width. Generate the msb and lsb
* expressions to get the canonical range for the given width.
*/
static vector<PExpr*>* make_range_vector(uint64_t wid)
{
vector<PExpr*>*tmp = new vector<PExpr*> (2);
tmp->at(0) = new PENumber(new verinum(wid-1, integer_width));
tmp->at(1) = new PENumber(new verinum((uint64_t)0, integer_width));
return tmp;
}
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
static list<perm_string>* list_from_identifier(char*id)
{
list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make(id));
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]id;
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
return tmp;
}
static list<perm_string>* list_from_identifier(list<perm_string>*tmp, char*id)
{
tmp->push_back(lex_strings.make(id));
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]id;
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
return tmp;
}
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
static list<PExpr*>* copy_range(list<PExpr*>* orig)
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
{
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*copy = 0;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
if (orig)
copy = new list<PExpr*> (*orig);
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
return copy;
}
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
template <class T> void append(vector<T>&out, const vector<T>&in)
{
for (size_t idx = 0 ; idx < in.size() ; idx += 1)
out.push_back(in[idx]);
}
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
/*
* This is a shorthand for making a PECallFunction that takes a single
* arg. This is used by some of the code that detects built-ins.
*/
static PECallFunction*make_call_function(perm_string tn, PExpr*arg)
{
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
vector<PExpr*> parms(1);
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
parms[0] = arg;
PECallFunction*tmp = new PECallFunction(tn, parms);
return tmp;
}
static PECallFunction*make_call_function(perm_string tn, PExpr*arg1, PExpr*arg2)
{
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
vector<PExpr*> parms(2);
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
parms[0] = arg1;
parms[1] = arg2;
PECallFunction*tmp = new PECallFunction(tn, parms);
return tmp;
}
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
static list<named_pexpr_t>* make_named_numbers(perm_string name, long first, long last, PExpr*val =0)
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
{
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*lst = new list<named_pexpr_t>;
named_pexpr_t tmp;
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
// We are counting up.
if (first <= last) {
for (long idx = first ; idx <= last ; idx += 1) {
ostringstream buf;
buf << name.str() << idx << ends;
tmp.name = lex_strings.make(buf.str());
tmp.parm = val;
val = 0;
lst->push_back(tmp);
}
// We are counting down.
} else {
for (long idx = first ; idx >= last ; idx -= 1) {
ostringstream buf;
buf << name.str() << idx << ends;
tmp.name = lex_strings.make(buf.str());
tmp.parm = val;
val = 0;
lst->push_back(tmp);
}
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
}
return lst;
}
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
static list<named_pexpr_t>* make_named_number(perm_string name, PExpr*val =0)
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
{
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*lst = new list<named_pexpr_t>;
named_pexpr_t tmp;
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
tmp.name = name;
tmp.parm = val;
lst->push_back(tmp);
return lst;
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
}
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
static long check_enum_seq_value(const YYLTYPE&loc, verinum *arg, bool zero_ok)
{
long value = 1;
// We can never have an undefined value in an enumeration name
// declaration sequence.
if (! arg->is_defined()) {
yyerror(loc, "error: undefined value used in enum name sequence.");
// We can never have a negative value in an enumeration name
// declaration sequence.
} else if (arg->is_negative()) {
yyerror(loc, "error: negative value used in enum name sequence.");
} else {
value = arg->as_ulong();
// We cannot have a zero enumeration name declaration count.
if (! zero_ok && (value == 0)) {
yyerror(loc, "error: zero count used in enum name sequence.");
value = 1;
}
}
return value;
}
System Verilog tasks can have multiple statements. The begin/end block that wraps the statements can be implicit.
2011-11-06 19:07:43 +01:00
static void current_task_set_statement(vector<Statement*>*s)
{
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
assert(s && !s->empty());
System Verilog tasks can have multiple statements. The begin/end block that wraps the statements can be implicit.
2011-11-06 19:07:43 +01:00
if (s->size() == 1) {
current_task->set_statement((*s)[0]);
return;
}
PBlock*tmp = new PBlock(PBlock::BL_SEQ);
tmp->set_statement(*s);
current_task->set_statement(tmp);
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
%}
%union {
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
bool flag;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
char letter;
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
int int_val;
Add ranges and signed to port list declarations.
2002-05-20 04:06:01 +02:00
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
/* text items are C strings allocated by the lexor using
strdup. They can be put into lists with the texts type. */
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
char*text;
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
list<perm_string>*perm_strings;
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
list<pair<perm_string,PExpr*> >*port_list;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
pform_name_t*pform_name;
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
Bring signal discipline all the way to the ivl_target API. Signals may have VMA disciplines attached. Make the attached discipline visible through the ivl_target.h API. Also, re-arrange the internal handling of the discipline structure so that we can expose disciplines through the ivl_target C API without creating new structures. The t-dll-api implementations of the discipline access functions can look at the elaborated discipline structure directly. This is possible since the discipline parse and elaboration are very simple.
2008-11-02 17:10:41 +01:00
ivl_discipline_t discipline;
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
hname_t*hier;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
list<string>*strings;
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
struct str_pair_t drive;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
PCase::Item*citem;
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
svector<PCase::Item*>*citems;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
lgate*gate;
Get rid of list<lgate> types.
1999-05-06 06:37:17 +02:00
svector<lgate>*gates;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
Module::port_t *mport;
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
LexicalScope::range_t* value_range;
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
vector<Module::port_t*>*mports;
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
named_number_t* named_number;
list<named_number_t>* named_numbers;
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
named_pexpr_t*named_pexpr;
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
list<named_pexpr_t>*named_pexprs;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
struct parmvalue_t*parmvalue;
module parameter bind by name.
1999-05-29 04:36:17 +02:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
PExpr*expr;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*exprs;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
svector<PEEvent*>*event_expr;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
NetNet::Type nettype;
PGBuiltin::Type gatetype;
NetNet::PortType porttype;
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
ivl_variable_type_t datatype;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
PWire*wire;
parse more verilog.
1999-06-12 22:35:27 +02:00
svector<PWire*>*wires;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
PEventStatement*event_statement;
Statement*statement;
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
vector<Statement*>*statement_list;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
PTaskFuncArg function_type;
Support integer for function return value.
2001-12-07 06:03:13 +01:00
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
net_decl_assign_t*net_decl_assign;
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
enum_type_t*enum_type;
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
decl_assignment_t*decl_assignment;
list<decl_assignment_t*>*decl_assignments;
struct_member_t*struct_member;
list<struct_member_t*>*struct_members;
struct_type_t*struct_type;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
data_type_t*data_type;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
verinum* number;
Add lexical support for real numbers.
1999-06-15 04:50:02 +02:00
verireal* realtime;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
PSpecPath* specpath;
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
list<index_component_t> *dimensions;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
};
Use user defined types in the syntax. Given that the syntax is already parsed and elaborated, it is a simple matter to bind that typedef'ed type to the instances that use it.
2012-01-16 02:29:18 +01:00
%token <text> IDENTIFIER SYSTEM_IDENTIFIER STRING TIME_LITERAL
%token <data_type> TYPE_IDENTIFIER
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
%token <discipline> DISCIPLINE_IDENTIFIER
Parse specparam parsepulse assignments.
2001-11-06 03:52:19 +01:00
%token <text> PATHPULSE_IDENTIFIER
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
%token <number> BASED_NUMBER DEC_NUMBER
Add lexical support for real numbers.
1999-06-15 04:50:02 +02:00
%token <realtime> REALTIME
Add support for increment and decrement operators This patch adds support for increment/decrement operators as an expression. The operations on real and vector slices have been disabled for now. These operators can be used as in independent statements. However, the corresponding support is not added in parser. Changes since V2: - Additional error checking in elaboration to deny operation on vector slices and real (suggested by Martin) Changes since V1: - Use 'i' and 'I' for increment (suggested by Cary) - Evaluate sub-expression once (suggested by Cary and Stev) - Add necessary checks during elaboration to ensure that the expression is valid (suggested Stev) - Proper width handling with vectors (suggested by Martin) Signed-off-by: Prasad Joshi <prasad@canopusconsultancy.com>
2011-08-06 23:54:38 +02:00
%token K_PLUS_EQ K_MINUS_EQ K_INCR K_DECR
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
%token K_LE K_GE K_EG K_EQ K_NE K_CEQ K_CNE K_LP K_LS K_RS K_RSS K_SG
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
/* K_CONTRIBUTE is <+, the contribution assign. */
%token K_CONTRIBUTE
Add support for power in constant expressions.
2006-07-31 05:50:17 +02:00
%token K_PO_POS K_PO_NEG K_POW
Wildcard named port connections. Implements Section 23.3.2.4 of IEEE 1800-2009.
2009-11-26 18:39:21 +01:00
%token K_PSTAR K_STARP K_DOTSTAR
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
%token K_LOR K_LAND K_NAND K_NOR K_NXOR K_TRIGGER
Fix some keywords, add -g2001-noconfig and fix up uwire/wone. This patch adds -g2001-noconfig command line flag. The compiler already supported this with `begin_keywords. Document this in the manual page and fix a few other issues. Fix endgenerate to be a 2001 keyword and add a few missing keywords at the appropriate standard level e.g.(unsigned). Add uwire and deprecate wone. wone used to just convert without a warning to a wire. uwire will display a warning that it is being converted to a wire without a check. wone is converted to a uwire with a warning and then prints the uwire message. The uwire message will be replaced with a real check fairly soon.
2009-06-02 02:19:56 +02:00
%token K_edge_descriptor
/* The base tokens from 1364-1995. */
%token K_always K_and K_assign K_begin K_buf K_bufif0 K_bufif1 K_case
%token K_casex K_casez K_cmos K_deassign K_default K_defparam K_disable
%token K_edge K_else K_end K_endcase K_endfunction K_endmodule
%token K_endprimitive K_endspecify K_endtable K_endtask K_event K_for
%token K_force K_forever K_fork K_function K_highz0 K_highz1 K_if
%token K_ifnone K_initial K_inout K_input K_integer K_join K_large
%token K_macromodule K_medium K_module K_nand K_negedge K_nmos K_nor
%token K_not K_notif0 K_notif1 K_or K_output K_parameter K_pmos K_posedge
%token K_primitive K_pull0 K_pull1 K_pulldown K_pullup K_rcmos K_real
%token K_realtime K_reg K_release K_repeat K_rnmos K_rpmos K_rtran
%token K_rtranif0 K_rtranif1 K_scalared K_small K_specify K_specparam
%token K_strong0 K_strong1 K_supply0 K_supply1 K_table K_task K_time
%token K_tran K_tranif0 K_tranif1 K_tri K_tri0 K_tri1 K_triand K_trior
%token K_trireg K_vectored K_wait K_wand K_weak0 K_weak1 K_while K_wire
%token K_wor K_xnor K_xor
Parse all the 1364-1995 and 1364-2001 timing checks. This patch adds code to parse and ignore the following timing checks: $nochange 1364-1995 $skew 1364-1995 $fullskew 1364-2001 $removal 1364-2001 $timeskew 1364-2001 The other checks were already supported. These have not been tested, but they use the same basic terms as the other checks. We can fully test these when we actually implement them.
2009-06-04 00:02:32 +02:00
%token K_Shold K_Snochange K_Speriod K_Srecovery K_Ssetup K_Ssetuphold
%token K_Sskew K_Swidth
Fix some keywords, add -g2001-noconfig and fix up uwire/wone. This patch adds -g2001-noconfig command line flag. The compiler already supported this with `begin_keywords. Document this in the manual page and fix a few other issues. Fix endgenerate to be a 2001 keyword and add a few missing keywords at the appropriate standard level e.g.(unsigned). Add uwire and deprecate wone. wone used to just convert without a warning to a wire. uwire will display a warning that it is being converted to a wire without a check. wone is converted to a uwire with a warning and then prints the uwire message. The uwire message will be replaced with a real check fairly soon.
2009-06-02 02:19:56 +02:00
/* Icarus specific tokens. */
%token KK_attribute K_bool K_logic
/* The new tokens from 1364-2001. */
%token K_automatic K_endgenerate K_generate K_genvar K_localparam
%token K_noshowcancelled K_pulsestyle_onevent K_pulsestyle_ondetect
%token K_showcancelled K_signed K_unsigned
Parse all the 1364-1995 and 1364-2001 timing checks. This patch adds code to parse and ignore the following timing checks: $nochange 1364-1995 $skew 1364-1995 $fullskew 1364-2001 $removal 1364-2001 $timeskew 1364-2001 The other checks were already supported. These have not been tested, but they use the same basic terms as the other checks. We can fully test these when we actually implement them.
2009-06-04 00:02:32 +02:00
%token K_Sfullskew K_Srecrem K_Sremoval K_Stimeskew
Fix some keywords, add -g2001-noconfig and fix up uwire/wone. This patch adds -g2001-noconfig command line flag. The compiler already supported this with `begin_keywords. Document this in the manual page and fix a few other issues. Fix endgenerate to be a 2001 keyword and add a few missing keywords at the appropriate standard level e.g.(unsigned). Add uwire and deprecate wone. wone used to just convert without a warning to a wire. uwire will display a warning that it is being converted to a wire without a check. wone is converted to a uwire with a warning and then prints the uwire message. The uwire message will be replaced with a real check fairly soon.
2009-06-02 02:19:56 +02:00
/* The 1364-2001 configuration tokens. */
%token K_cell K_config K_design K_endconfig K_incdir K_include K_instance
%token K_liblist K_library K_use
/* The new tokens from 1364-2005. */
%token K_wone K_uwire
Add a generation for 1800-2005, etc. It was a poor choice to only add -g2009 for 1800-2009 and ignore the previous version of System Verilog 1800-2005. This patch adds a generation for 1800-2005 and also adds `begin_keywords support for 1800-2005. The previous SystemVerilog keywords have been put under the 1800-2005 generation and the new one from 1800-2009 have also been added.
2011-01-09 00:35:52 +01:00
/* The new tokens from 1800-2005. */
Add all the SystemVerilog (1800-2005) keywords. This patch adds the SystemVerilog keywords to Icarus. This allows use to easily verify that out plain Verilog does not contain any SystemVerilog keywords. The keywords are not parsed in any way. When parsing a Verilog file using -gsystem-verilog any identifier that is a keyword will cause a parse error. It is the users responsibility to figure out the problem since bison does not give nice error message when it finds a keyword instead of an identifier.
2010-01-19 04:06:01 +01:00
%token K_alias K_always_comb K_always_ff K_always_latch K_assert
%token K_assume K_before K_bind K_bins K_binsof K_bit K_break K_byte
%token K_chandle K_class K_clocking K_const K_constraint K_context
%token K_continue K_cover K_covergroup K_coverpoint K_cross K_dist K_do
%token K_endclass K_endclocking K_endgroup K_endinterface K_endpackage
%token K_endprogram K_endproperty K_endsequence K_enum K_expect K_export
%token K_extends K_extern K_final K_first_match K_foreach K_forkjoin
%token K_iff K_ignore_bins K_illegal_bins K_import K_inside K_int
/* Icarus already has defined "logic" above! */
%token K_interface K_intersect K_join_any K_join_none K_local
%token K_longint K_matches K_modport K_new K_null K_package K_packed
%token K_priority K_program K_property K_protected K_pure K_rand K_randc
%token K_randcase K_randsequence K_ref K_return K_sequence K_shortint
Add all the Verilog-AMS 2.3.1 keywords. Like I did for SystemVerilog the other day this patch adds all the Verilog-AMS 2.3.1 keywords. This necessitated adding one my byte to the gperf -k argument (byte 9) to make the laplace_?? tokens have a unique hash.
2010-01-21 02:35:38 +01:00
%token K_shortreal K_solve K_static K_string K_struct K_super
Add all the SystemVerilog (1800-2005) keywords. This patch adds the SystemVerilog keywords to Icarus. This allows use to easily verify that out plain Verilog does not contain any SystemVerilog keywords. The keywords are not parsed in any way. When parsing a Verilog file using -gsystem-verilog any identifier that is a keyword will cause a parse error. It is the users responsibility to figure out the problem since bison does not give nice error message when it finds a keyword instead of an identifier.
2010-01-19 04:06:01 +01:00
%token K_tagged K_this K_throughout K_timeprecision K_timeunit K_type
%token K_typedef K_union K_unique K_var K_virtual K_void K_wait_order
%token K_wildcard K_with K_within
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
/* Fake tokens that are passed once we have an initial token. */
%token K_timeprecision_check K_timeunit_check
Added gsystem-verilog gen flag and 4 additional keywords For future system-verilog additions
2009-01-10 10:02:09 +01:00
Add a generation for 1800-2005, etc. It was a poor choice to only add -g2009 for 1800-2009 and ignore the previous version of System Verilog 1800-2005. This patch adds a generation for 1800-2005 and also adds `begin_keywords support for 1800-2005. The previous SystemVerilog keywords have been put under the 1800-2005 generation and the new one from 1800-2009 have also been added.
2011-01-09 00:35:52 +01:00
/* The new tokens from 1800-2009. */
%token K_accept_on K_checker K_endchecker K_eventually K_global K_implies
%token K_let K_nexttime K_reject_on K_restrict K_s_always K_s_eventually
%token K_s_nexttime K_s_until K_s_until_with K_strong K_sync_accept_on
%token K_sync_reject_on K_unique0 K_until K_until_with K_untyped K_weak
Fix some keywords, add -g2001-noconfig and fix up uwire/wone. This patch adds -g2001-noconfig command line flag. The compiler already supported this with `begin_keywords. Document this in the manual page and fix a few other issues. Fix endgenerate to be a 2001 keyword and add a few missing keywords at the appropriate standard level e.g.(unsigned). Add uwire and deprecate wone. wone used to just convert without a warning to a wire. uwire will display a warning that it is being converted to a wire without a check. wone is converted to a uwire with a warning and then prints the uwire message. The uwire message will be replaced with a real check fairly soon.
2009-06-02 02:19:56 +02:00
/* The new tokens for Verilog-AMS 2.3. */
Add all the Verilog-AMS 2.3.1 keywords. Like I did for SystemVerilog the other day this patch adds all the Verilog-AMS 2.3.1 keywords. This necessitated adding one my byte to the gperf -k argument (byte 9) to make the laplace_?? tokens have a unique hash.
2010-01-21 02:35:38 +01:00
%token K_above K_abs K_absdelay K_abstol K_access K_acos K_acosh
/* 1800-2005 has defined "assert" above! */
%token K_ac_stim K_aliasparam K_analog K_analysis K_asin K_asinh
%token K_atan K_atan2 K_atanh K_branch K_ceil K_connect K_connectmodule
%token K_connectrules K_continuous K_cos K_cosh K_ddt K_ddt_nature K_ddx
%token K_discipline K_discrete K_domain K_driver_update K_endconnectrules
%token K_enddiscipline K_endnature K_endparamset K_exclude K_exp
%token K_final_step K_flicker_noise K_floor K_flow K_from K_ground
%token K_hypot K_idt K_idtmod K_idt_nature K_inf K_initial_step
%token K_laplace_nd K_laplace_np K_laplace_zd K_laplace_zp
%token K_last_crossing K_limexp K_ln K_log K_max K_merged K_min K_nature
%token K_net_resolution K_noise_table K_paramset K_potential K_pow
/* 1800-2005 has defined "string" above! */
%token K_resolveto K_sin K_sinh K_slew K_split K_sqrt K_tan K_tanh
%token K_timer K_transition K_units K_white_noise K_wreal
%token K_zi_nd K_zi_np K_zi_zd K_zi_zp
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
%type <flag> from_exclude
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
%type <number> number pos_neg_number
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
%type <flag> unsigned_signed_opt signed_unsigned_opt
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
%type <flag> K_automatic_opt K_packed_opt K_reg_opt K_virtual_opt
%type <flag> udp_reg_opt edge_operator
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
%type <drive> drive_strength drive_strength_opt dr_strength0 dr_strength1
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
%type <letter> udp_input_sym udp_output_sym
%type <text> udp_input_list udp_sequ_entry udp_comb_entry
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
%type <perm_strings> udp_input_declaration_list
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
%type <strings> udp_entry_list udp_comb_entry_list udp_sequ_entry_list
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
%type <strings> udp_body
%type <perm_strings> udp_port_list
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
%type <wires> udp_port_decl udp_port_decls
%type <statement> udp_initial udp_init_opt
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
%type <expr> udp_initial_expr_opt
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
Parse program blocks / Fix module end-name syntax.
2012-02-18 19:02:54 +01:00
%type <text> register_variable net_variable real_variable endname_opt
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
%type <perm_strings> register_variable_list net_variable_list
%type <perm_strings> real_variable_list list_of_identifiers
%type <port_list> list_of_port_identifiers
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
%type <net_decl_assign> net_decl_assign net_decl_assigns
Net declaration assignments.
1999-06-02 04:56:29 +02:00
Fix handling of inline decloration without wire keyword.
2003-02-08 00:16:09 +01:00
%type <mport> port port_opt port_reference port_reference_list
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
%type <mport> port_declaration
Blind support for "integer foreign" attributes. (Stefan Theide) Allows iverilog to parse attribute like syntax that a common simuator puts into automatically generated verilog code. This syntax cannot be found in any of the IEEE standards.
2009-02-24 01:37:34 +01:00
%type <mports> list_of_ports module_port_list_opt list_of_port_declarations module_attribute_foreign
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
%type <value_range> parameter_value_range parameter_value_ranges
%type <value_range> parameter_value_ranges_opt
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
%type <expr> tf_port_item_expr_opt value_range_expression
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
%type <named_pexprs> enum_name_list enum_name
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
%type <enum_type> enum_data_type
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
%type <wires> task_item task_item_list task_item_list_opt
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
%type <wires> task_port_item tf_port_item tf_port_list tf_port_list_opt
Add functions up to elaboration (Ed Carter)
1999-07-31 21:14:47 +02:00
%type <wires> function_item function_item_list
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
%type <named_pexpr> port_name parameter_value_byname
%type <named_pexprs> port_name_list parameter_value_byname_list
%type <named_pexpr> attribute
Allows multiple attribute instances. This patch adds the ability to have multiple attribute instances (e.g. (* foo = 1 *) (* bar = 2 *)).
2011-02-25 02:37:56 +01:00
%type <named_pexprs> attribute_list attribute_instance_list attribute_list_opt
module parameter bind by name.
1999-05-29 04:36:17 +02:00
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
%type <citem> case_item
%type <citems> case_items
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
%type <gate> gate_instance
%type <gates> gate_instance_list
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
%type <pform_name> hierarchy_identifier
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
%type <expr> assignment_pattern expression expr_primary expr_mintypmax
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
%type <expr> inc_or_dec_expression lpvalue
Parse contribution statements as far as pform. Contribution statements have an l-value and r-value. Parse those expressions into pform so that elaboration has something to work with. In this process, this patch also changes the PECallFunction class to use the vector template instead of the svector template. The latter doesn't add anything over the STL vector template, so this is a start of working the svector out.
2008-07-27 23:22:19 +02:00
%type <expr> branch_probe_expression
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
%type <expr> delay_value delay_value_simple
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
%type <exprs> delay1 delay3 delay3_opt delay_value_list
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
%type <exprs> expression_list_with_nuls expression_list_proper
Rename assign_list to cont_assign_list.
2007-04-21 06:45:36 +02:00
%type <exprs> cont_assign cont_assign_list
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
%type <decl_assignment> variable_decl_assignment
%type <decl_assignments> list_of_variable_decl_assignments
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
%type <data_type> data_type
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
%type <struct_member> struct_union_member
%type <struct_members> struct_union_member_list
%type <struct_type> struct_data_type
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
%type <exprs> range range_opt variable_dimension
Remove shift/reduce problems from dimensions patch. This patch needs to be applied after the dimensions checking patch to remove the shift/reduce errors it created.
2007-11-14 05:49:05 +01:00
%type <dimensions> dimensions_opt dimensions
Fix handling of inline decloration without wire keyword.
2003-02-08 00:16:09 +01:00
%type <nettype> net_type var_type net_type_opt
The switch gates do not support a strength specification. This patch splits the switch types out of the gates to allow them to be defined to not take a strength specification.
2010-07-14 01:12:03 +02:00
%type <gatetype> gatetype switchtype
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
%type <porttype> port_direction port_direction_opt
Allow 'bit' and 'logic' function arguments SystemVerilog allows passing the 'bit' and 'logic' arguments to a function. The patch adds support for parsing these function definitions. The 'bit' data type is treated as boolean, whereas 'logic' data type remains as logic. Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-07 15:41:22 +02:00
%type <datatype> primitive_type primitive_type_opt bit_logic
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
%type <parmvalue> parameter_value_opt
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
%type <function_type> function_range_or_type_opt
Fix shift/reduce warnings and ?:. (dhn@qedinc.com)
1999-09-30 00:56:31 +02:00
%type <event_expr> event_expression_list
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
%type <event_expr> event_expression
%type <event_statement> event_control
Add support for C-like assignments operators SystemVerilog extended the assignments operator support to C-like assignment operators and special bitwise assignment operators. For example: a += 1; a -= 1; The list of these operators can be found in SV LRM (1800-2009) section 11.4.1. NOTE: I fixed a few parts of this. In particular, the PEBShift class is used for shift operators. Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-21 04:03:24 +02:00
%type <statement> statement statement_or_null compressed_statement
Parse for declarations, implement for_step statements. for-statement declarations still generate a "sorry" message, but the for_step statements work in general now.
2012-02-25 18:28:20 +01:00
%type <statement> loop_statement for_step
System Verilog tasks can have multiple statements. The begin/end block that wraps the statements can be implicit.
2011-11-06 19:07:43 +01:00
%type <statement_list> statement_list statement_or_null_list
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
%type <statement_list> statement_list_or_null
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Basic elaboration of analog contribution statements. Get at least basic elaboration of analog processes and contribution statements. Bring the statements and analog statements together and net future elaboration work sort out which statements are valid in a given context. This makes sense because there really is a lot of syntactic overlap, and analog behavioral code is processed somewhat sequentially.
2008-10-23 06:56:00 +02:00
%type <statement> analog_statement
Infrastructure for parsing analog process statements. Organize the parsing infrastructure for parsing analog processes, including holding them in scopes, and collecting analog statements.
2008-07-27 21:02:09 +02:00
specparams as far as pform.
2003-02-27 07:45:11 +01:00
%type <letter> spec_polarity
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
%type <perm_strings> specify_path_identifiers
specparams as far as pform.
2003-02-27 07:45:11 +01:00
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
%type <specpath> specify_simple_path specify_simple_path_decl
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
%type <specpath> specify_edge_path specify_edge_path_decl
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
%type <int_val> atom2_type
Parse program blocks / Fix module end-name syntax.
2012-02-18 19:02:54 +01:00
%type <int_val> module_start module_end
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
%token K_TAND
Add support for C-like assignments operators SystemVerilog extended the assignments operator support to C-like assignment operators and special bitwise assignment operators. For example: a += 1; a -= 1; The list of these operators can be found in SV LRM (1800-2009) section 11.4.1. NOTE: I fixed a few parts of this. In particular, the PEBShift class is used for shift operators. Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-21 04:03:24 +02:00
%right K_PLUS_EQ K_MINUS_EQ K_MUL_EQ K_DIV_EQ K_MOD_EQ K_AND_EQ K_OR_EQ
%right K_XOR_EQ K_LS_EQ K_RS_EQ K_RSS_EQ
Fix shift/reduce warnings and ?:. (dhn@qedinc.com)
1999-09-30 00:56:31 +02:00
%right '?' ':'
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
%left K_LOR
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
%left K_LAND
%left '|'
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
%left '^' K_NXOR K_NOR
%left '&' K_NAND
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
%left K_EQ K_NE K_CEQ K_CNE
%left K_GE K_LE '<' '>'
Add arithmetic shift operators.
2003-06-18 05:55:18 +02:00
%left K_LS K_RS K_RSS
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
%left '+' '-'
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
%left '*' '/' '%'
Add support for power in constant expressions.
2006-07-31 05:50:17 +02:00
%left K_POW
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
%left UNARY_PREC
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Add support for exclude of a point Parameter value ranges support the exclude of a point as well as range, so add the syntax to support that case. Internally it is handled as a degenerate range, but the parse and initial elaboration need to know about it.
2008-06-06 06:49:49 +02:00
Add ANSI style parameter port declarations.
2003-12-19 06:15:04 +01:00
/* to resolve dangling else ambiguity. */
Fix shift/reduce warnings and ?:. (dhn@qedinc.com)
1999-09-30 00:56:31 +02:00
%nonassoc less_than_K_else
%nonassoc K_else
Add support for exclude of a point Parameter value ranges support the exclude of a point as well as range, so add the syntax to support that case. Internally it is handled as a degenerate range, but the parse and initial elaboration need to know about it.
2008-06-06 06:49:49 +02:00
/* to resolve exclude (... ambiguity */
%nonassoc '('
%nonassoc K_exclude
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
%%
Parse empty source files.
1999-10-15 07:03:33 +02:00
/* A degenerate source file can be completely empty. */
main : source_file | ;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
source_file
: description
| source_file description
;
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
assignment_pattern /* IEEE1800-2005: A.6.7.1 */
: K_LP expression_list_proper '}'
{ PEVoid*tmp = new PEVoid;
FILE_NAME(tmp, @1);
yyerror(@1, "sorry: Assignment patterns (array literals) not supported.");
$$ = tmp;
}
| K_LP '}'
{ PEVoid*tmp = new PEVoid;
FILE_NAME(tmp, @1);
yyerror(@1, "sorry: Assignment patterns (array literals) not supported.");
$$ = tmp;
}
;
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
class_declaration /* IEEE1800-2005: A.1.2 */
: K_virtual_opt K_class IDENTIFIER ';'
class_items_opt K_endclass endname_opt
{ // Process a class
if ($7 && strcmp($3,$7)!=0) {
yyerror(@7, "error: Class end name doesn't match class name.");
delete[]$7;
}
yyerror(@2, "sorry: Class declarations not supported yet.");
}
;
class_items_opt
: class_items
|
;
class_items
: class_items class_item
| class_item
;
class_item /* IEEE1800-2005: A.1.8 */
/* class_constructor_declaration */
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
: K_function K_new '(' tf_port_list_opt ')' ';'
statement_list_or_null
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
K_endfunction endnew_opt
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
{ yyerror(@1, "sorry: Class constructors not supported yet.");
yyerrok;
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
/* Class properties... */
| data_type list_of_variable_decl_assignments ';'
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
/* Class methods... */
| task_declaration
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
/* Here are some error matching rules to help recover from various
syntax errors within a class declaration. */
| K_function K_new error K_endfunction endnew_opt
{ yyerror(@1, "error: I give up on this class constructor declaration.");
yyerrok;
}
;
data_type /* IEEE1800-2005: A.2.2.1 */
: struct_data_type
{ $$ = $1; }
| enum_data_type
{ $$ = $1; }
| atom2_type signed_unsigned_opt
{ atom2_type_t*tmp = new atom2_type_t($1, $2);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| TYPE_IDENTIFIER
{ $$ = $1; }
| K_string
{ yyerror(@1, "sorry: String data type not supported.");
$$ = 0;
}
;
endnew_opt : ':' K_new | ;
Parse for declarations, implement for_step statements. for-statement declarations still generate a "sorry" message, but the for_step statements work in general now.
2012-02-25 18:28:20 +01:00
for_step /* IEEE1800-2005: A.6.8 */
: lpvalue '=' expression
{ PAssign*tmp = new PAssign($1,$3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| inc_or_dec_expression
{ $$ = pform_compressed_assign_from_inc_dec(@1, $1); }
| compressed_statement
{ $$ = $1; }
;
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
implicit_class_handle /* IEEE1800-2005: A.8.4 */
: K_this
| K_super
;
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
/* SystemVerilog adds support for the increment/decrement
expressions, which look like a++, --a, etc. These are primaries
but are in their own rules because they can also be
statements. Note that the operator can only take l-value
expressions. */
inc_or_dec_expression /* IEEE1800-2005: A.4.3 */
: K_INCR lpvalue %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('I', $2);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| lpvalue K_INCR %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('i', $1);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| K_DECR lpvalue %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('D', $2);
FILE_NAME(tmp, @2);
$$ = tmp;
}
| lpvalue K_DECR %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('d', $1);
FILE_NAME(tmp, @1);
$$ = tmp;
}
;
Parse for declarations, implement for_step statements. for-statement declarations still generate a "sorry" message, but the for_step statements work in general now.
2012-02-25 18:28:20 +01:00
/* Loop statements are kinds of statements. */
loop_statement /* IEEE1800-2005: A.6.8 */
: K_for '(' lpvalue '=' expression ';' expression ';' for_step ')'
statement_or_null
{ PForStatement*tmp = new PForStatement($3, $5, $7, $9, $11);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| K_for '(' data_type IDENTIFIER '=' expression ';' expression ';' for_step ')'
statement_or_null
{ $$ = 0;
yyerror(@3, "sorry: for_variable_declaration not supported");
}
| K_forever statement_or_null
{ PForever*tmp = new PForever($2);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| K_repeat '(' expression ')' statement_or_null
{ PRepeat*tmp = new PRepeat($3, $5);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| K_while '(' expression ')' statement_or_null
{ PWhile*tmp = new PWhile($3, $5);
FILE_NAME(tmp, @1);
$$ = tmp;
}
/* Error forms for loop statements. */
| K_for '(' lpvalue '=' expression ';' expression ';' error ')'
statement_or_null
{ $$ = 0;
yyerror(@1, "error: Error in for loop step assignment.");
}
| K_for '(' lpvalue '=' expression ';' error ';' for_step ')'
statement_or_null
{ $$ = 0;
yyerror(@1, "error: Error in for loop condition expression.");
}
| K_for '(' error ')' statement_or_null
{ $$ = 0;
yyerror(@1, "error: Incomprehensible for loop.");
}
| K_while '(' error ')' statement_or_null
{ $$ = 0;
yyerror(@1, "error: Error in while loop condition.");
}
;
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
number : BASED_NUMBER
Check for extra digits in sized binary, octal and hex constants. Print out a warning if extra digits are given for sized binary, octal or hex constants. Decimal constants are very hard since we never calculate the true number of bits the digits represent, so for now decimal constants are not checked.
2007-10-12 01:37:57 +02:00
{ $$ = $1; based_size = 0;}
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
| DEC_NUMBER
Check for extra digits in sized binary, octal and hex constants. Print out a warning if extra digits are given for sized binary, octal or hex constants. Decimal constants are very hard since we never calculate the true number of bits the digits represent, so for now decimal constants are not checked.
2007-10-12 01:37:57 +02:00
{ $$ = $1; based_size = 0;}
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
| DEC_NUMBER BASED_NUMBER
Check for extra digits in sized binary, octal and hex constants. Print out a warning if extra digits are given for sized binary, octal or hex constants. Decimal constants are very hard since we never calculate the true number of bits the digits represent, so for now decimal constants are not checked.
2007-10-12 01:37:57 +02:00
{ $$ = pform_verinum_with_size($1,$2, @2.text, @2.first_line);
based_size = 0; }
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
;
Non-controversial whitespace cleanup Nothing to do with tab width! Eliminates useless trailing spaces and tabs, and nearly all <space><tab> pairings. No change to derived files (e.g., .vvp), non-master files (e.g., lxt2_write.c) or the new tgt-vhdl directory. Low priority, simple entropy reduction. Please apply unless it deletes some steganographic content you want to keep.
2008-09-04 18:41:51 +02:00
/* real and realtime are exactly the same so save some code
User task and function arguments can be time or realtime This patch adds the time and realtime properties for user task and function arguments. It also make a common rule for real and realtime since they are the same.
2008-08-09 03:12:52 +02:00
* with a common matching rule. */
real_or_realtime
: K_real
| K_realtime
;
Parse for declarations, implement for_step statements. for-statement declarations still generate a "sorry" message, but the for_step statements work in general now.
2012-02-25 18:28:20 +01:00
/* Many places where statements are allowed can actually take a
statement or a null statement marked with a naked semi-colon. */
statement_or_null /* IEEE1800-2005: A.6.4 */
: statement
{ $$ = $1; }
| ';'
{ $$ = 0; }
;
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
/* The task declaration rule matches the task declaration
header, then pushes the function scope. This causes the
definitions in the task_body to take on the scope of the task
instead of the module. */
task_declaration /* IEEE1800-2005: A.2.7 */
: K_task K_automatic_opt IDENTIFIER ';'
{ assert(current_task == 0);
current_task = pform_push_task_scope(@1, $3, $2);
}
task_item_list_opt
statement_or_null_list
K_endtask
{ current_task->set_ports($6);
current_task_set_statement($7);
pform_pop_scope();
current_task = 0;
if ($7->size() > 1 && !gn_system_verilog()) {
yyerror(@7, "error: Task body with multiple statements requres SystemVerilog.");
}
delete $7;
}
System Verilog supports closing names after endtask keyword.
2012-02-25 02:04:49 +01:00
endname_opt
{ // Last step: check any closing name. This is done late so
// that the parser can look ahead to detect the present
// endname_opt but still have the pform_endmodule() called
// early enough that the lexor can know we are outside the
// module.
if ($10 && (strcmp($3,$10) != 0)) {
yyerror(@10, "error: End name doesn't match module/program name");
}
if ($10 && !gn_system_verilog()) {
yyerror(@10, "error: Task end names require System Verilog.");
}
delete[]$3;
if ($10) delete[]$10;
}
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
| K_task K_automatic_opt IDENTIFIER '('
{ assert(current_task == 0);
current_task = pform_push_task_scope(@1, $3, $2);
}
tf_port_list ')' ';'
block_item_decls_opt
statement_or_null_list
K_endtask
{ current_task->set_ports($6);
current_task_set_statement($10);
pform_pop_scope();
current_task = 0;
if ($10->size() > 1 && !gn_system_verilog()) {
yyerror(@10, "error: Task body with multiple statements requres SystemVerilog.");
}
delete $10;
}
System Verilog supports closing names after endtask keyword.
2012-02-25 02:04:49 +01:00
endname_opt
{ // Last step: check any closing name. This is done late so
// that the parser can look ahead to detect the present
// endname_opt but still have the pform_endmodule() called
// early enough that the lexor can know we are outside the
// module.
if ($13 && (strcmp($3,$13) != 0)) {
yyerror(@13, "error: End name doesn't match module/program name");
}
if ($13 && !gn_system_verilog()) {
yyerror(@13, "error: Task end names require System Verilog.");
}
delete[]$3;
if ($13) delete[]$13;
}
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
| K_task K_automatic_opt IDENTIFIER '(' ')' ';'
{ assert(current_task == 0);
current_task = pform_push_task_scope(@1, $3, $2);
}
block_item_decls_opt
statement_or_null_list
K_endtask
{ current_task->set_ports(0);
current_task_set_statement($9);
pform_pop_scope();
current_task = 0;
cerr << @3 << ": warning: task definition for \"" << $3
<< "\" has an empty port declaration list!" << endl;
if ($9->size() > 1 && !gn_system_verilog()) {
yyerror(@9, "error: Task body with multiple statements requres SystemVerilog.");
}
delete $9;
}
System Verilog supports closing names after endtask keyword.
2012-02-25 02:04:49 +01:00
endname_opt
{ // Last step: check any closing name. This is done late so
// that the parser can look ahead to detect the present
// endname_opt but still have the pform_endmodule() called
// early enough that the lexor can know we are outside the
// module.
if ($12 && (strcmp($3,$12) != 0)) {
yyerror(@12, "error: End name doesn't match module/program name");
}
if ($12 && !gn_system_verilog()) {
yyerror(@12, "error: Task end names require System Verilog.");
}
delete[]$3;
if ($12) delete[]$12;
}
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
| K_task K_automatic_opt IDENTIFIER error K_endtask
{
assert(current_task == 0);
System Verilog supports closing names after endtask keyword.
2012-02-25 02:04:49 +01:00
}
endname_opt
{ // Last step: check any closing name. This is done late so
// that the parser can look ahead to detect the present
// endname_opt but still have the pform_endmodule() called
// early enough that the lexor can know we are outside the
// module.
if ($7 && (strcmp($3,$7) != 0)) {
yyerror(@7, "error: End name doesn't match module/program name");
}
if ($7 && !gn_system_verilog()) {
yyerror(@7, "error: Task end names require System Verilog.");
}
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
delete[]$3;
System Verilog supports closing names after endtask keyword.
2012-02-25 02:04:49 +01:00
if ($7) delete[]$7;
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
}
;
/* These rules for tf_port_item are slightly expanded from the
strict rules in the LRM to help with LALR parsing.
NOTE: Some of these rules should be folded into the "data_type"
variant which uses the data_type rule to match data type
declarations. That some rules do not use the data_type production
is a consequence of legacy. */
tf_port_item /* IEEE1800-2005: A.2.7 */
: port_direction K_reg_opt unsigned_signed_opt range_opt IDENTIFIER range_opt tf_port_item_expr_opt
{ port_declaration_context.port_type = $1;
port_declaration_context.var_type = IVL_VT_LOGIC;
port_declaration_context.sign_flag = $3;
delete port_declaration_context.range;
port_declaration_context.range = copy_range($4);
svector<PWire*>*tmp = pform_make_task_ports(@5, $1, IVL_VT_LOGIC, $3,
$4, list_from_identifier($5));
$$ = tmp;
if ($6) {
yyerror(@6, "sorry: Port variable dimensions not supported yet.");
delete $6;
}
if ($7) {
yyerror(@7, "sorry: Port default expressions not supported yet.");
delete $7;
}
}
| port_direction_opt bit_logic unsigned_signed_opt range_opt IDENTIFIER range_opt tf_port_item_expr_opt
{ port_declaration_context.port_type = $1;
port_declaration_context.var_type = $2;
port_declaration_context.sign_flag = $3;
delete port_declaration_context.range;
port_declaration_context.range = copy_range($4);
svector<PWire*>*tmp = pform_make_task_ports(@5, $1, $2, $3,
$4, list_from_identifier($5));
$$ = tmp;
if ($6) {
yyerror(@6, "sorry: Port variable dimensions not supported yet.");
delete $6;
}
if ($7) {
yyerror(@7, "sorry: Port default expressions not supported yet.");
delete $7;
}
}
/* Ports can be integer with a width of [31:0]. */
| port_direction_opt K_integer IDENTIFIER range_opt tf_port_item_expr_opt
{ list<PExpr*>*range_stub = make_range_from_width(integer_width);
port_declaration_context.port_type = $1;
port_declaration_context.var_type = IVL_VT_LOGIC;
port_declaration_context.sign_flag = true;
delete port_declaration_context.range;
port_declaration_context.range = copy_range(range_stub);
svector<PWire*>*tmp = pform_make_task_ports(@3, $1, IVL_VT_LOGIC, true,
range_stub,
list_from_identifier($3), true);
$$ = tmp;
if ($4) {
yyerror(@4, "sorry: Port variable dimensions not supported yet.");
delete $4;
}
if ($5) {
yyerror(@5, "sorry: Port default expressions not supported yet.");
delete $5;
}
}
/* Ports can be time with a width of [63:0] (unsigned). */
| port_direction_opt K_time IDENTIFIER range_opt tf_port_item_expr_opt
{ list<PExpr*>*range_stub = make_range_from_width(64);
port_declaration_context.port_type = $1;
port_declaration_context.var_type = IVL_VT_LOGIC;
port_declaration_context.sign_flag = false;
delete port_declaration_context.range;
port_declaration_context.range = copy_range(range_stub);
svector<PWire*>*tmp = pform_make_task_ports(@3, $1, IVL_VT_LOGIC, false,
range_stub,
list_from_identifier($3));
$$ = tmp;
if ($4) {
yyerror(@4, "sorry: Port variable dimensions not supported yet.");
delete $4;
}
if ($5) {
yyerror(@5, "sorry: Port default expressions not supported yet.");
delete $5;
}
}
/* Ports can be real or realtime. */
| port_direction_opt real_or_realtime IDENTIFIER range_opt tf_port_item_expr_opt
{ port_declaration_context.port_type = $1;
port_declaration_context.var_type = IVL_VT_REAL;
port_declaration_context.sign_flag = false;
delete port_declaration_context.range;
port_declaration_context.range = 0;
svector<PWire*>*tmp = pform_make_task_ports(@3, $1, IVL_VT_REAL, false,
0, list_from_identifier($3));
$$ = tmp;
if ($4) {
yyerror(@4, "sorry: Port variable dimensions not supported yet.");
delete $4;
}
if ($5) {
yyerror(@5, "sorry: Port default expressions not supported yet.");
delete $5;
}
}
| port_direction_opt data_type IDENTIFIER range_opt tf_port_item_expr_opt
{ port_declaration_context.port_type = $1;
port_declaration_context.var_type = IVL_VT_NO_TYPE;
port_declaration_context.sign_flag = false;
delete port_declaration_context.range;
port_declaration_context.range = 0;
port_declaration_context.data_type = $2;
svector<PWire*>*tmp = pform_make_task_ports(@3, $1, $2,
list_from_identifier($3));
$$ = tmp;
if ($4) {
yyerror(@4, "sorry: Port variable dimensions not supported yet.");
delete $4;
}
if ($5) {
yyerror(@5, "sorry: Port default expressions not supported yet.");
delete $5;
}
}
;
/* This rule matches the [ = <expression> ] part of the tf_port_item rules. */
tf_port_item_expr_opt
: '=' expression { $$ = $2; }
| { $$ = 0; }
;
tf_port_list /* IEEE1800-2005: A.2.7 */
: tf_port_list ',' tf_port_item
{ svector<PWire*>*tmp;
if ($3) {
tmp = new svector<PWire*>(*$1, *$3);
delete $1;
delete $3;
} else {
tmp = $1;
}
$$ = tmp;
}
| tf_port_item
{ $$ = $1; }
/* This rule handles the special case of a set of port items leading
an undecorated identifier. Undeconated identifiers in this case
pick up the details from the list to its lift. */
| tf_port_list ',' IDENTIFIER
{ // The declaration is already parsed, apply it to IDENTIFIER
svector<PWire*>*new_decl;
if (port_declaration_context.var_type == IVL_VT_NO_TYPE) {
assert(port_declaration_context.data_type);
new_decl = pform_make_task_ports(@3, port_declaration_context.port_type,
port_declaration_context.data_type,
list_from_identifier($3));
} else {
new_decl = pform_make_task_ports(@3, port_declaration_context.port_type,
port_declaration_context.var_type,
port_declaration_context.sign_flag,
copy_range(port_declaration_context.range),
list_from_identifier($3));
}
svector<PWire*>*tmp = new svector<PWire*>(*$1, *new_decl);
delete $1;
delete new_decl;
$$ = tmp;
}
/* Rules to handle some errors in tf_port_list items. */
| error ',' tf_port_item
{ yyerror(@2, "error: Syntax error in task/function port declaration.");
$$ = $3;
}
| tf_port_list ','
{ yyerror(@2, "error: NULL port declarations are not allowed.");
$$ = $1;
}
| tf_port_list ';'
{ yyerror(@2, "error: ';' is an invalid port declaration separator.");
$$ = $1;
}
;
variable_dimension /* IEEE1800-2005: A.2.5 */
: '[' expression ':' expression ']'
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($2);
tmp->push_back($4);
$$ = tmp;
}
| '[' ']'
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back(0);
tmp->push_back(0);
$$ = tmp;
}
;
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
/* Verilog-2001 supports attribute lists, which can be attached to a
variety of different objects. The syntax inside the (* *) is a
comma separated list of names or names with assigned values. */
attribute_list_opt
Allows multiple attribute instances. This patch adds the ability to have multiple attribute instances (e.g. (* foo = 1 *) (* bar = 2 *)).
2011-02-25 02:37:56 +01:00
: attribute_instance_list
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
| { $$ = 0; }
;
Allows multiple attribute instances. This patch adds the ability to have multiple attribute instances (e.g. (* foo = 1 *) (* bar = 2 *)).
2011-02-25 02:37:56 +01:00
attribute_instance_list
: K_PSTAR K_STARP { $$ = 0; }
| K_PSTAR attribute_list K_STARP { $$ = $2; }
| attribute_instance_list K_PSTAR K_STARP { $$ = $1; }
| attribute_instance_list K_PSTAR attribute_list K_STARP
{ list<named_pexpr_t>*tmp = $1;
if (tmp) {
tmp->splice(tmp->end(), *$3);
delete $3;
$$ = tmp;
} else $$ = $3;
}
;
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
attribute_list
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
: attribute_list ',' attribute
{ list<named_pexpr_t>*tmp = $1;
tmp->push_back(*$3);
delete $3;
$$ = tmp;
}
| attribute
{ list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
tmp->push_back(*$1);
delete $1;
$$ = tmp;
}
;
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
attribute
: IDENTIFIER
{ named_pexpr_t*tmp = new named_pexpr_t;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp->name = lex_strings.make($1);
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
tmp->parm = 0;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
$$ = tmp;
}
| IDENTIFIER '=' expression
{ PExpr*tmp = $3;
named_pexpr_t*tmp2 = new named_pexpr_t;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp2->name = lex_strings.make($1);
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
tmp2->parm = tmp;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
$$ = tmp2;
}
;
Handle declaration of integers (including scope) in functions.
1999-09-30 03:22:37 +02:00
/* The block_item_decl is used in function definitions, task
definitions, module definitions and named blocks. Wherever a new
scope is entered, the source may declare new registers and
integers. This rule matches those declarations. The containing
rule has presumably set up the scope. */
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
block_item_decl
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
: attribute_list_opt K_reg
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
primitive_type_opt unsigned_signed_opt range
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
register_variable_list ';'
{ ivl_variable_type_t dtype = $3;
if (dtype == IVL_VT_NO_TYPE)
dtype = IVL_VT_LOGIC;
pform_set_net_range($6, $5, $4, dtype);
Parse attributes attached to reg declarations.
2004-09-14 20:24:56 +02:00
if ($1) delete $1;
Handle integers at task parameters.
1999-09-10 07:02:09 +02:00
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
/* This differs from the above pattern only in the absence of the
range. This is the rule for a scalar. */
| attribute_list_opt K_reg
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
primitive_type_opt unsigned_signed_opt
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
register_variable_list ';'
{ ivl_variable_type_t dtype = $3;
if (dtype == IVL_VT_NO_TYPE)
dtype = IVL_VT_LOGIC;
pform_set_net_range($5, 0, $4, dtype);
Parse attributes attached to reg declarations.
2004-09-14 20:24:56 +02:00
if ($1) delete $1;
Detect the signed keyword.
2000-04-02 06:25:39 +02:00
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Add support for variable of primitive data type 'bit' Verilog allows user to define variables of primitive types. The patch adds support for defining variables of type 'bit'. The data type 'bit' is the only primitive data type which supports defining ranges. Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-06-28 17:43:21 +02:00
| attribute_list_opt K_bit unsigned_signed_opt range_opt
register_variable_list ';'
{
pform_set_net_range($5, $4, $3, IVL_VT_BOOL);
if ($1) delete $1;
}
Add support for variable of primitive data type 'logic' Verilog allows user to define variables of primitive types. The patch adds support for defining variables of type 'logic'. The data type 'logic' is the only primitive data type which supports defining ranges. Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-06-28 15:59:02 +02:00
| attribute_list_opt K_logic unsigned_signed_opt range_opt
register_variable_list ';'
{
pform_set_net_range($5, $4, $3, IVL_VT_LOGIC);
if ($1) delete $1;
}
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
/* Integer atom declarations are simpler in that they do not have
all the trappings of a general variable declaration. All of that
is implicit in the "integer" of the declaration. */
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
| attribute_list_opt K_integer signed_unsigned_opt register_variable_list ';'
{ pform_set_reg_integer($4);
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
if ($1) delete $1;
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
| attribute_list_opt K_time register_variable_list ';'
{ pform_set_reg_time($3);
if ($1) delete $1;
}
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
/* variable declarations. Note that data_type can be 0 if we are
recovering from an error. */
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
| attribute_list_opt data_type register_variable_list ';'
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
{ if ($2) pform_set_data_type(@2, $2, $3);
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
if ($1) delete $1;
}
Remove NetVariable and ivl_variable_t structures.
2005-07-11 18:56:50 +02:00
/* real declarations are fairly simple as there is no range of
signed flag in the declaration. Create the real as a NetNet::REG
Spelling fixes Mostly comments, but includes quite a few user-visible error, debug, and help messages.
2008-06-12 19:04:29 +02:00
with real value. Note that real and realtime are interchangeable
Remove NetVariable and ivl_variable_t structures.
2005-07-11 18:56:50 +02:00
in this context. */
Support for automatic tasks and functions. This patch adds support for automatic tasks and functions. Refer to the overview in vvp/README.txt for details.
2008-09-27 01:54:13 +02:00
| attribute_list_opt K_real real_variable_list ';'
{ delete $3; }
| attribute_list_opt K_realtime real_variable_list ';'
{ delete $3; }
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Support parameter, localparam, and event declarations in any scope. Currently, parameters and localparams declared in tasks, functions, generate blocks, and named blocks are placed in the parent module scope. Event declarations in these scopes are not permitted (a syntax error is reported). This patch corrects this behaviour, so that all the above declarations are accepted and are placed in the scope in which they are declared. Note that the IEEE standard does not permit parameter declarations in generate blocks. This patch causes the parser to reject such declarations.
2008-09-17 22:25:59 +02:00
| K_event list_of_identifiers ';'
{ pform_make_events($2, @1.text, @1.first_line);
}
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
| K_parameter parameter_assign_decl ';'
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
| K_localparam localparam_assign_decl ';'
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
/* Blocks can have type declarations. */
| type_declaration
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
/* Recover from errors that happen within variable lists. Use the
trailing semi-colon to resync the parser. */
Parse attributes attached to reg declarations.
2004-09-14 20:24:56 +02:00
| attribute_list_opt K_reg error ';'
{ yyerror(@2, "error: syntax error in reg variable list.");
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
yyerrok;
Parse attributes attached to reg declarations.
2004-09-14 20:24:56 +02:00
if ($1) delete $1;
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
}
Parse attributes attached to reg declarations.
2004-09-14 20:24:56 +02:00
| attribute_list_opt K_integer error ';'
{ yyerror(@2, "error: syntax error in integer variable list.");
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
yyerrok;
Parse attributes attached to reg declarations.
2004-09-14 20:24:56 +02:00
if ($1) delete $1;
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
}
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
| attribute_list_opt K_time error ';'
{ yyerror(@2, "error: syntax error in time variable list.");
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
yyerrok;
}
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
| attribute_list_opt K_real error ';'
{ yyerror(@2, "error: syntax error in real variable list.");
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
yyerrok;
}
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
| attribute_list_opt K_realtime error ';'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@2, "error: syntax error in realtime variable list.");
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
yyerrok;
}
Parse parameters within nested scopes.
2001-01-13 23:20:08 +01:00
| K_parameter error ';'
{ yyerror(@1, "error: syntax error in parameter list.");
yyerrok;
}
| K_localparam error ';'
{ yyerror(@1, "error: syntax error localparam list.");
yyerrok;
}
Handle expression widths for EEE and NEE operators, add named blocks and scope handling, add registers declared in named blocks.
1999-06-24 06:24:18 +02:00
;
block_item_decls
: block_item_decl
| block_item_decls block_item_decl
;
block_item_decls_opt
: block_item_decls
|
;
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
/* Type declarations are parsed here. The rule actions call pform
functions that add the declaration to the current lexical scope. */
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
type_declaration
: K_typedef data_type IDENTIFIER ';'
Implement simple typedefs, and parse type identifiers. This gets me to the point where the parser stashes a defined type, and the lexical analyzer uses the type names to differentiate IDENTIFIER and TYPE_IDENTIFIER.
2012-01-09 02:51:18 +01:00
{ perm_string name = lex_strings.make($3);
pform_set_typedef(name, $2);
delete[]$3;
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
/* These are forward declarations... */
| K_typedef K_class IDENTIFIER ';'
{ yyerror(@1, "sorry: Class forward declarations not supported yet.") }
| K_typedef K_enum IDENTIFIER ';'
{ yyerror(@1, "sorry: Enum forward declarations not supported yet.") }
| K_typedef K_struct IDENTIFIER ';'
{ yyerror(@1, "sorry: Struct forward declarations not supported yet.") }
| K_typedef K_union IDENTIFIER ';'
{ yyerror(@1, "sorry: Union forward declarations not supported yet.") }
| K_typedef IDENTIFIER ';'
{ yyerror(@1, "sorry: Class forward declarations not supported yet.") }
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
;
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
/* The structure for an enumeration data type is the keyword "enum",
followed by the enumeration values in curly braces. Also allow
for an optional base type. The default base type is "int", but it
can be any of the integral or vector types. */
enum_data_type
: K_enum '{' enum_name_list '}'
{ enum_type_t*enum_type = new enum_type_t;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
FILE_NAME(enum_type, @1);
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
enum_type->names .reset($3);
enum_type->base_type = IVL_VT_BOOL;
enum_type->signed_flag = true;
enum_type->range.reset( make_range_from_width(32) );
$$ = enum_type;
}
| K_enum atom2_type signed_unsigned_opt '{' enum_name_list '}'
{ enum_type_t*enum_type = new enum_type_t;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
FILE_NAME(enum_type, @1);
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
enum_type->names .reset($5);
enum_type->base_type = IVL_VT_BOOL;
enum_type->signed_flag = $3;
enum_type->range.reset( make_range_from_width($2) );
$$ = enum_type;
}
| K_enum K_integer signed_unsigned_opt '{' enum_name_list '}'
{ enum_type_t*enum_type = new enum_type_t;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
FILE_NAME(enum_type, @1);
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
enum_type->names .reset($5);
enum_type->base_type = IVL_VT_LOGIC;
enum_type->signed_flag = $3;
enum_type->range.reset( make_range_from_width(integer_width) );
$$ = enum_type;
}
Fix some enum bugs. This patch fixes a few more bugs in the enumeration code. It add support for saving the file and line information to make diagnostic messages better. It updates some of the compiler warning messages to use the file and line information. It passes if the enumeration type is signed all the way to the code generators. It fixes the parser to correctly have the range after the signed designation for the vector types. It adds a warning that vvp does not currently support a negative two state enumeration value.
2011-09-01 23:29:40 +02:00
| K_enum K_logic unsigned_signed_opt range '{' enum_name_list '}'
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
{ enum_type_t*enum_type = new enum_type_t;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
FILE_NAME(enum_type, @1);
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
enum_type->names .reset($6);
enum_type->base_type = IVL_VT_LOGIC;
Fix some enum bugs. This patch fixes a few more bugs in the enumeration code. It add support for saving the file and line information to make diagnostic messages better. It updates some of the compiler warning messages to use the file and line information. It passes if the enumeration type is signed all the way to the code generators. It fixes the parser to correctly have the range after the signed designation for the vector types. It adds a warning that vvp does not currently support a negative two state enumeration value.
2011-09-01 23:29:40 +02:00
enum_type->signed_flag = $3;
enum_type->range.reset( $4 );
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
$$ = enum_type;
}
Fix some enum bugs. This patch fixes a few more bugs in the enumeration code. It add support for saving the file and line information to make diagnostic messages better. It updates some of the compiler warning messages to use the file and line information. It passes if the enumeration type is signed all the way to the code generators. It fixes the parser to correctly have the range after the signed designation for the vector types. It adds a warning that vvp does not currently support a negative two state enumeration value.
2011-09-01 23:29:40 +02:00
| K_enum K_reg unsigned_signed_opt range '{' enum_name_list '}'
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
{ enum_type_t*enum_type = new enum_type_t;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
FILE_NAME(enum_type, @1);
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
enum_type->names .reset($6);
enum_type->base_type = IVL_VT_LOGIC;
Fix some enum bugs. This patch fixes a few more bugs in the enumeration code. It add support for saving the file and line information to make diagnostic messages better. It updates some of the compiler warning messages to use the file and line information. It passes if the enumeration type is signed all the way to the code generators. It fixes the parser to correctly have the range after the signed designation for the vector types. It adds a warning that vvp does not currently support a negative two state enumeration value.
2011-09-01 23:29:40 +02:00
enum_type->signed_flag = $3;
enum_type->range.reset( $4 );
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
$$ = enum_type;
}
Fix some enum bugs. This patch fixes a few more bugs in the enumeration code. It add support for saving the file and line information to make diagnostic messages better. It updates some of the compiler warning messages to use the file and line information. It passes if the enumeration type is signed all the way to the code generators. It fixes the parser to correctly have the range after the signed designation for the vector types. It adds a warning that vvp does not currently support a negative two state enumeration value.
2011-09-01 23:29:40 +02:00
| K_enum K_bit unsigned_signed_opt range '{' enum_name_list '}'
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
{ enum_type_t*enum_type = new enum_type_t;
Parse simple typedefs Parse typedefs with structs and enums, but give a sorry message, because they are not yet supported. Rearrange some of the parse rules for variables in order to increase comonality with the typedef rules.
2012-01-08 00:37:30 +01:00
FILE_NAME(enum_type, @1);
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
enum_type->names .reset($6);
enum_type->base_type = IVL_VT_BOOL;
Fix some enum bugs. This patch fixes a few more bugs in the enumeration code. It add support for saving the file and line information to make diagnostic messages better. It updates some of the compiler warning messages to use the file and line information. It passes if the enumeration type is signed all the way to the code generators. It fixes the parser to correctly have the range after the signed designation for the vector types. It adds a warning that vvp does not currently support a negative two state enumeration value.
2011-09-01 23:29:40 +02:00
enum_type->signed_flag = $3;
enum_type->range.reset( $4 );
Support enum base type vectors Including bit/reg/logic types.
2010-11-13 04:28:43 +01:00
$$ = enum_type;
}
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
;
enum_name_list
: enum_name
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
{ $$ = $1;
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
}
| enum_name_list ',' enum_name
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
{ list<named_pexpr_t>*lst = $1;
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
lst->splice(lst->end(), *$3);
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
delete $3;
$$ = lst;
}
;
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
pos_neg_number
: number
{ $$ = $1;
}
| '-' number
{ verinum tmp = v_not(*($2)) + verinum(1);
*($2) = tmp;
$$ = $2;
}
;
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
enum_name
: IDENTIFIER
{ perm_string name = lex_strings.make($1);
delete[]$1;
$$ = make_named_number(name);
}
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
| IDENTIFIER '[' pos_neg_number ']'
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
{ perm_string name = lex_strings.make($1);
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
long count = check_enum_seq_value(@1, $3, false);
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
delete[]$1;
$$ = make_named_numbers(name, 0, count-1);
delete $3;
}
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
| IDENTIFIER '[' pos_neg_number ':' pos_neg_number ']'
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
{ perm_string name = lex_strings.make($1);
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
$$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
check_enum_seq_value(@1, $5, true));
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
delete[]$1;
delete $3;
delete $5;
}
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
| IDENTIFIER '=' expression
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
{ perm_string name = lex_strings.make($1);
delete[]$1;
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
$$ = make_named_number(name, $3);
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
}
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
| IDENTIFIER '[' pos_neg_number ']' '=' expression
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
{ perm_string name = lex_strings.make($1);
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
long count = check_enum_seq_value(@1, $3, false);
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
$$ = make_named_numbers(name, 0, count-1, $6);
delete[]$1;
delete $3;
}
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
| IDENTIFIER '[' pos_neg_number ':' pos_neg_number ']' '=' expression
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
{ perm_string name = lex_strings.make($1);
Add more enumeration sequence name error checking. This patch adds code to check for a negative or undefined value used in an enumeration sequence name, it verifies that the count in an enumeration sequence name is not zero and allows more decimal constant values in the enumeration sequence name..
2011-07-21 05:46:27 +02:00
$$ = make_named_numbers(name, check_enum_seq_value(@1, $3, true),
check_enum_seq_value(@1, $5, true), $8);
Support enumeration element ranges. This also fixes: Set verinum.has_sign() correctly for enum values.
2010-11-10 06:05:47 +01:00
delete[]$1;
delete $3;
delete $5;
}
Finish up parser code for enum types This gets the parser syntax actions done, up to the pform code. It is ready for generating pform structures.
2010-10-24 20:21:17 +02:00
;
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
struct_data_type
: K_struct K_packed_opt '{' struct_union_member_list '}'
{ struct_type_t*tmp = new struct_type_t;
FILE_NAME(tmp, @1);
tmp->packed_flag = $2;
tmp->members .reset($4);
$$ = tmp;
}
| K_struct K_packed_opt '{' error '}'
{ yyerror(@4, "error: Errors in struct/union member list.");
yyerrok;
struct_type_t*tmp = new struct_type_t;
FILE_NAME(tmp, @1);
tmp->packed_flag = $2;
$$ = tmp;
}
;
struct_union_member_list
: struct_union_member_list struct_union_member
{ list<struct_member_t*>*tmp = $1;
tmp->push_back($2);
$$ = tmp;
}
| struct_union_member
{ list<struct_member_t*>*tmp = new list<struct_member_t*>;
Handle members of packed struct as implicit part selects. Packed struct members are synonymous with part selects, but in a much more convenient form, so get them to work that way.
2011-12-11 19:28:04 +01:00
tmp->push_back($1);
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
$$ = tmp;
}
;
struct_union_member
: attribute_list_opt K_bit range_opt list_of_variable_decl_assignments ';'
{ struct_member_t*tmp = new struct_member_t;
FILE_NAME(tmp, @2);
tmp->type = IVL_VT_BOOL;
tmp->range .reset($3);
tmp->names .reset($4);
$$ = tmp;
}
| attribute_list_opt K_logic range_opt list_of_variable_decl_assignments ';'
{ struct_member_t*tmp = new struct_member_t;
FILE_NAME(tmp, @2);
tmp->type = IVL_VT_LOGIC;
tmp->range .reset($3);
tmp->names .reset($4);
$$ = tmp;
}
| attribute_list_opt atom2_type list_of_variable_decl_assignments ';'
{ struct_member_t*tmp = new struct_member_t;
FILE_NAME(tmp, @2);
tmp->type = IVL_VT_BOOL;
tmp->range .reset( make_range_from_width($2) );
tmp->names .reset($3);
$$ = tmp;
}
;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
case_item
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
: expression_list_proper ':' statement_or_null
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
{ PCase::Item*tmp = new PCase::Item;
Support case expression lists.
1999-06-15 07:38:39 +02:00
tmp->expr = *$1;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
tmp->stat = $3;
Support case expression lists.
1999-06-15 07:38:39 +02:00
delete $1;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_default ':' statement_or_null
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
{ PCase::Item*tmp = new PCase::Item;
tmp->stat = $3;
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_default statement_or_null
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
{ PCase::Item*tmp = new PCase::Item;
tmp->stat = $2;
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| error ':' statement_or_null
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@2, "error: Incomprehensible case expression.");
More parseable syntax.
1999-06-12 05:42:57 +02:00
yyerrok;
}
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
;
case_items
: case_items case_item
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
{ svector<PCase::Item*>*tmp;
tmp = new svector<PCase::Item*>(*$1, $2);
delete $1;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
$$ = tmp;
}
| case_item
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
{ svector<PCase::Item*>*tmp = new svector<PCase::Item*>(1);
(*tmp)[0] = $1;
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
$$ = tmp;
}
;
Add lexical support for real numbers.
1999-06-15 04:50:02 +02:00
charge_strength
: '(' K_small ')'
| '(' K_medium ')'
| '(' K_large ')'
;
charge_strength_opt
: charge_strength
|
;
More syntax parse with sorry stubs.
1999-06-16 05:13:29 +02:00
defparam_assign
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
: hierarchy_identifier '=' expression
Remove checks for constant expressions from the parser. This patch removes all the checks for constant expressions performed during the parsing phase, as these checks are (mostly) repeated during elaboration. It adds the missing check in the elaboration phase (the RHS of a register initialisation), and improves the error reporting and error recovery in other checks. This patch fixes pr2132552, which was caused by a fault in the parser constant expression checking.
2008-10-04 16:30:34 +02:00
{ pform_set_defparam(*$1, $3);
More syntax parse with sorry stubs.
1999-06-16 05:13:29 +02:00
delete $1;
}
;
defparam_assign_list
: defparam_assign
| range defparam_assign
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
{ yyerror(@1, "error: defparam may not include a range.");
More syntax parse with sorry stubs.
1999-06-16 05:13:29 +02:00
delete $1;
}
| defparam_assign_list ',' defparam_assign
;
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
delay1
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
: '#' delay_value_simple
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($2);
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
$$ = tmp;
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
}
delay1 expressions can take parentheses.
1999-12-31 18:39:00 +01:00
| '#' '(' delay_value ')'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($3);
delay1 expressions can take parentheses.
1999-12-31 18:39:00 +01:00
$$ = tmp;
}
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
;
delay3
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
: '#' delay_value_simple
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($2);
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
$$ = tmp;
}
| '#' '(' delay_value ')'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($3);
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
$$ = tmp;
}
| '#' '(' delay_value ',' delay_value ')'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($3);
tmp->push_back($5);
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
$$ = tmp;
}
| '#' '(' delay_value ',' delay_value ',' delay_value ')'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($3);
tmp->push_back($5);
tmp->push_back($7);
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
$$ = tmp;
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
}
;
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
delay3_opt
: delay3 { $$ = $1; }
| { $$ = 0; }
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
delay_value_list
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
: delay_value
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($1);
$$ = tmp;
}
| delay_value_list ',' delay_value
{ list<PExpr*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
delay_value
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
: expression
{ PExpr*tmp = $1;
$$ = tmp;
}
| expression ':' expression ':' expression
Introduce min:typ:max support.
2000-07-29 19:58:20 +02:00
{ $$ = pform_select_mtm_expr($1, $3, $5); }
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
;
Clean up spurious trailing white space.
2004-10-04 03:10:51 +02:00
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
delay_value_simple
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
: DEC_NUMBER
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
{ verinum*tmp = $1;
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
if (tmp == 0) {
Standardize error/sorry messages.
1999-09-29 23:16:32 +02:00
yyerror(@1, "internal error: delay.");
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
$$ = 0;
} else {
$$ = new PENumber(tmp);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME($$, @1);
Support sized decimal numbers, Fix operator precedence order.
1999-03-16 05:44:45 +01:00
}
Fix a small bug in the extra digits warning. There were a couple places where a normal decimal number was accidentally setting the base for an unsized number. This is only a warning problem.
2008-03-06 01:36:27 +01:00
based_size = 0;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Support decimal constants in behavioral delays.
2000-12-10 23:01:35 +01:00
| REALTIME
{ verireal*tmp = $1;
if (tmp == 0) {
yyerror(@1, "internal error: delay.");
$$ = 0;
} else {
$$ = new PEFNumber(tmp);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME($$, @1);
Support decimal constants in behavioral delays.
2000-12-10 23:01:35 +01:00
}
}
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
| IDENTIFIER
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ PEIdent*tmp = new PEIdent(lex_strings.make($1));
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse more things.
1999-05-08 22:19:20 +02:00
$$ = tmp;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
}
Add support for SystemVerilog style time literals SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-05 19:11:56 +02:00
| TIME_LITERAL
Make call to pow() unambiguous pow(int, int) is ambiguous since it could use the double version from the math library or the verinum version. This patch makes it obvious that we want to use the double version.
2011-07-18 23:19:32 +02:00
{ int unit;
based_size = 0;
$$ = 0;
if ($1 == 0 || !get_time_unit($1, unit))
yyerror(@1, "internal error: delay.");
else {
double p = pow(10.0,
(double)(unit - pform_get_timeunit()));
double time = atof($1) * p;
verireal *v = new verireal(time);
$$ = new PEFNumber(v);
FILE_NAME($$, @1);
}
Add support for SystemVerilog style time literals SystemVerilog has support for time literals. The time literal for example #10ns, adds a delay of 10ns no matter the time unit currently in effect. For more details please refer to http://iverilog.wikia.com/wiki/Projects#SystemVerilog_Style_Time_Literals Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-05 19:11:56 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
description
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
: module
| udp_primitive
Parse the config declarations and report they will be ignored. This patch adds code to parse config declarations and reports that they are not currently supported and will be ignored.
2009-06-13 01:21:20 +02:00
| config_declaration
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
| nature_declaration
| discipline_declaration
| KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')'
{ perm_string tmp3 = lex_strings.make($3);
pform_set_type_attrib(tmp3, $5, $7);
Make lexical token STRING new based. The STRING lexical token was malloc based, but then was passed to routines that are expecting a new based result. This patch standardizes on a new/delete based approach.
2009-01-09 02:03:33 +01:00
delete[] $3;
delete[] $5;
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
}
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
| K_timeunit TIME_LITERAL ';'
{ pform_set_timeunit($2, false, false); }
| K_timeprecision TIME_LITERAL ';'
{ pform_set_timeprecision($2, false, false); }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
;
Make semi-colon after discipline/nature name optional. The VAMS-2.2 LRM syntax does not include a semicolon after the nature/ discipline name, but the 2.3 LRM does. Effectively, that means that the simicolon is option from now on.
2008-05-13 02:31:59 +02:00
/* The discipline and nature declarations used to take no ';' after
the identifier. The 2.3 LRM adds the ';', but since there are
programs written to the 2.1 and 2.2 standard that don't, we
choose to make the ';' optional in this context. */
optional_semicolon : ';' | ;
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
discipline_declaration
Make semi-colon after discipline/nature name optional. The VAMS-2.2 LRM syntax does not include a semicolon after the nature/ discipline name, but the 2.3 LRM does. Effectively, that means that the simicolon is option from now on.
2008-05-13 02:31:59 +02:00
: K_discipline IDENTIFIER optional_semicolon
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
{ pform_start_discipline($2); }
discipline_items K_enddiscipline
{ pform_end_discipline(@1); delete[] $2; }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
;
discipline_items
: discipline_items discipline_item
| discipline_item
;
discipline_item
: K_domain K_discrete ';'
Bring signal discipline all the way to the ivl_target API. Signals may have VMA disciplines attached. Make the attached discipline visible through the ivl_target.h API. Also, re-arrange the internal handling of the discipline structure so that we can expose disciplines through the ivl_target C API without creating new structures. The t-dll-api implementations of the discipline access functions can look at the elaborated discipline structure directly. This is possible since the discipline parse and elaboration are very simple.
2008-11-02 17:10:41 +01:00
{ pform_discipline_domain(@1, IVL_DIS_DISCRETE); }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
| K_domain K_continuous ';'
Bring signal discipline all the way to the ivl_target API. Signals may have VMA disciplines attached. Make the attached discipline visible through the ivl_target.h API. Also, re-arrange the internal handling of the discipline structure so that we can expose disciplines through the ivl_target C API without creating new structures. The t-dll-api implementations of the discipline access functions can look at the elaborated discipline structure directly. This is possible since the discipline parse and elaboration are very simple.
2008-11-02 17:10:41 +01:00
{ pform_discipline_domain(@1, IVL_DIS_CONTINUOUS); }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
| K_potential IDENTIFIER ';'
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
{ pform_discipline_potential(@1, $2); delete[] $2; }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
| K_flow IDENTIFIER ';'
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
{ pform_discipline_flow(@1, $2); delete[] $2; }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
;
nature_declaration
Make semi-colon after discipline/nature name optional. The VAMS-2.2 LRM syntax does not include a semicolon after the nature/ discipline name, but the 2.3 LRM does. Effectively, that means that the simicolon is option from now on.
2008-05-13 02:31:59 +02:00
: K_nature IDENTIFIER optional_semicolon
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
{ pform_start_nature($2); }
Nature and discipline declarations syntax The VAMS-2.3 specification says that discipline and nature declarations have a semi-colon after the identifier, but the disciplines.vams in the appendix does not. Initial guess what that the disciplines.vams is correct, but I've been told that the syntax is correct and the disciplines.vams file is not.
2008-05-11 21:13:58 +02:00
nature_items
K_endnature
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
{ pform_end_nature(@1); delete[] $2; }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
;
nature_items
: nature_items nature_item
| nature_item
;
nature_item
: K_units '=' STRING ';'
{ delete[] $3; }
| K_abstol '=' expression ';'
| K_access '=' IDENTIFIER ';'
Attach natures to disciplines Pform parse enough of the natures that they can be mapped and the disciplines can bind to them. Since Verilog-AMS expects natures to be declared before use, we can do the binding early.
2008-05-12 03:52:27 +02:00
{ pform_nature_access(@1, $3); delete[] $3; }
Add disciplines.vams and enough syntax to parse it. This is part of the standard disciplines header file, with enough syntax to part the natures and disciplines included. Don't do anything with the parse results yet.
2008-05-10 19:37:33 +02:00
| K_idt_nature '=' IDENTIFIER ';'
{ delete[] $3; }
| K_ddt_nature '=' IDENTIFIER ';'
{ delete[] $3; }
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse the config declarations and report they will be ignored. This patch adds code to parse config declarations and reports that they are not currently supported and will be ignored.
2009-06-13 01:21:20 +02:00
config_declaration
: K_config IDENTIFIER ';'
K_design lib_cell_identifiers ';'
list_of_config_rule_statements
K_endconfig
{ cerr << @1 << ": sorry: config declarations are not supported and "
"will be skipped." << endl;
delete[] $2;
}
;
lib_cell_identifiers
: /* The BNF implies this can be blank, but I'm not sure exactly what
* this means. */
| lib_cell_identifiers lib_cell_id
;
list_of_config_rule_statements
: /* config rules are optional. */
| list_of_config_rule_statements config_rule_statement
;
config_rule_statement
: K_default K_liblist list_of_libraries ';'
| K_instance hierarchy_identifier K_liblist list_of_libraries ';'
{ delete $2; }
| K_instance hierarchy_identifier K_use lib_cell_id opt_config ';'
{ delete $2; }
| K_cell lib_cell_id K_liblist list_of_libraries ';'
| K_cell lib_cell_id K_use lib_cell_id opt_config ';'
;
opt_config
: /* The use clause takse an optional :config. */
| ':' K_config
lib_cell_id
: IDENTIFIER
{ delete[] $1; }
| IDENTIFIER '.' IDENTIFIER
{ delete[] $1; delete[] $3; }
;
list_of_libraries
: /* A NULL library means use the parents cell library. */
| list_of_libraries IDENTIFIER
{ delete[] $2; }
parse drive strengths.
1999-11-05 20:36:36 +01:00
drive_strength
: '(' dr_strength0 ',' dr_strength1 ')'
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
{ $$.str0 = $2.str0;
$$.str1 = $4.str1;
}
parse drive strengths.
1999-11-05 20:36:36 +01:00
| '(' dr_strength1 ',' dr_strength0 ')'
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
{ $$.str0 = $4.str0;
$$.str1 = $2.str1;
}
parse drive strengths.
1999-11-05 20:36:36 +01:00
| '(' dr_strength0 ',' K_highz1 ')'
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
{ $$.str0 = $2.str0;
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
$$.str1 = IVL_DR_HiZ;
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
}
parse drive strengths.
1999-11-05 20:36:36 +01:00
| '(' dr_strength1 ',' K_highz0 ')'
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
{ $$.str0 = IVL_DR_HiZ;
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
$$.str1 = $2.str1;
}
parse drive strengths.
1999-11-05 20:36:36 +01:00
| '(' K_highz1 ',' dr_strength0 ')'
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
{ $$.str0 = $4.str0;
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
$$.str1 = IVL_DR_HiZ;
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
}
parse drive strengths.
1999-11-05 20:36:36 +01:00
| '(' K_highz0 ',' dr_strength1 ')'
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
{ $$.str0 = IVL_DR_HiZ;
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
$$.str1 = $4.str1;
}
parse drive strengths.
1999-11-05 20:36:36 +01:00
;
drive_strength_opt
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
: drive_strength { $$ = $1; }
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
| { $$.str0 = IVL_DR_STRONG; $$.str1 = IVL_DR_STRONG; }
parse drive strengths.
1999-11-05 20:36:36 +01:00
;
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
dr_strength0
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
: K_supply0 { $$.str0 = IVL_DR_SUPPLY; }
| K_strong0 { $$.str0 = IVL_DR_STRONG; }
| K_pull0 { $$.str0 = IVL_DR_PULL; }
| K_weak0 { $$.str0 = IVL_DR_WEAK; }
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
;
dr_strength1
Remove Link::strength_t and PGate::strength_t types. These types are useless repetition of the ivl_drive_t type. This is also another chapter in the series to push ivl_target generation further upstream.
2010-03-16 23:16:53 +01:00
: K_supply1 { $$.str1 = IVL_DR_SUPPLY; }
| K_strong1 { $$.str1 = IVL_DR_STRONG; }
| K_pull1 { $$.str1 = IVL_DR_PULL; }
| K_weak1 { $$.str1 = IVL_DR_WEAK; }
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
;
parse drive strengths.
1999-11-05 20:36:36 +01:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
event_control
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
: '@' hierarchy_identifier
Allow named events to be referenced by hierarchical names.
2002-11-02 04:27:51 +01:00
{ PEIdent*tmpi = new PEIdent(*$2);
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
PEEvent*tmpe = new PEEvent(PEEvent::ANYEDGE, tmpi);
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
PEventStatement*tmps = new PEventStatement(tmpe);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmps, @1);
Named events as far as the pform.
2000-04-01 21:31:57 +02:00
$$ = tmps;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
delete $2;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Fix shift/reduce warnings and ?:. (dhn@qedinc.com)
1999-09-30 00:56:31 +02:00
| '@' '(' event_expression_list ')'
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
{ PEventStatement*tmp = new PEventStatement(*$3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
delete $3;
$$ = tmp;
}
| '@' '(' error ')'
Standardize error/sorry messages.
1999-09-29 23:16:32 +02:00
{ yyerror(@1, "error: Malformed event control expression.");
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
$$ = 0;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
;
Fix shift/reduce warnings and ?:. (dhn@qedinc.com)
1999-09-30 00:56:31 +02:00
event_expression_list
: event_expression
{ $$ = $1; }
| event_expression_list K_or event_expression
{ svector<PEEvent*>*tmp = new svector<PEEvent*>(*$1, *$3);
delete $1;
delete $3;
$$ = tmp;
}
fork-join support in vvm.
2000-04-15 21:51:30 +02:00
| event_expression_list ',' event_expression
{ svector<PEEvent*>*tmp = new svector<PEEvent*>(*$1, *$3);
delete $1;
delete $3;
$$ = tmp;
}
Fix shift/reduce warnings and ?:. (dhn@qedinc.com)
1999-09-30 00:56:31 +02:00
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
event_expression
: K_posedge expression
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
{ PEEvent*tmp = new PEEvent(PEEvent::POSEDGE, $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
svector<PEEvent*>*tl = new svector<PEEvent*>(1);
(*tl)[0] = tmp;
$$ = tl;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
| K_negedge expression
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
{ PEEvent*tmp = new PEEvent(PEEvent::NEGEDGE, $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
svector<PEEvent*>*tl = new svector<PEEvent*>(1);
(*tl)[0] = tmp;
$$ = tl;
}
| expression
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
{ PEEvent*tmp = new PEEvent(PEEvent::ANYEDGE, $1);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
svector<PEEvent*>*tl = new svector<PEEvent*>(1);
(*tl)[0] = tmp;
$$ = tl;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
/* A branch probe expression applies a probe function (potential or
flow) to a branch. The branch may be implicit as a pair of nets
or explicit as a named branch. Elaboration will check that the
function name really is a nature attribute identifier. */
branch_probe_expression
: IDENTIFIER '(' IDENTIFIER ',' IDENTIFIER ')'
Parse contribution statements as far as pform. Contribution statements have an l-value and r-value. Parse those expressions into pform so that elaboration has something to work with. In this process, this patch also changes the PECallFunction class to use the vector template instead of the svector template. The latter doesn't add anything over the STL vector template, so this is a start of working the svector out.
2008-07-27 23:22:19 +02:00
{ $$ = pform_make_branch_probe_expression(@1, $1, $3, $5); }
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
| IDENTIFIER '(' IDENTIFIER ')'
Parse contribution statements as far as pform. Contribution statements have an l-value and r-value. Parse those expressions into pform so that elaboration has something to work with. In this process, this patch also changes the PECallFunction class to use the vector template instead of the svector template. The latter doesn't add anything over the STL vector template, so this is a start of working the svector out.
2008-07-27 23:22:19 +02:00
{ $$ = pform_make_branch_probe_expression(@1, $1, $3); }
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
expression
: expr_primary
{ $$ = $1; }
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
| inc_or_dec_expression
{ $$ = $1; }
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
| '+' expr_primary %prec UNARY_PREC
More unary operators.
1999-06-13 19:30:23 +02:00
{ $$ = $2; }
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
| '-' expr_primary %prec UNARY_PREC
Line number information.
1999-05-27 05:31:29 +02:00
{ PEUnary*tmp = new PEUnary('-', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
}
| '~' expr_primary %prec UNARY_PREC
Line number information.
1999-05-27 05:31:29 +02:00
{ PEUnary*tmp = new PEUnary('~', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
| '&' expr_primary %prec UNARY_PREC
Line number information.
1999-05-27 05:31:29 +02:00
{ PEUnary*tmp = new PEUnary('&', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
| '!' expr_primary %prec UNARY_PREC
Line number information.
1999-05-27 05:31:29 +02:00
{ PEUnary*tmp = new PEUnary('!', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
}
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
| '|' expr_primary %prec UNARY_PREC
Line number information.
1999-05-27 05:31:29 +02:00
{ PEUnary*tmp = new PEUnary('|', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
}
| '^' expr_primary %prec UNARY_PREC
Line number information.
1999-05-27 05:31:29 +02:00
{ PEUnary*tmp = new PEUnary('^', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
}
Print a better error message for a '~' token in front of ('&' | '|' | '^') Some users may expect this to work so this patch catches these specific cases and tells the user to use the singe unary operators '~&', etc. instead.
2009-05-20 18:14:39 +02:00
| '~' '&' expr_primary %prec UNARY_PREC
{ yyerror(@1, "error: '~' '&' is not a valid expression. "
"Please use operator '~&' instead.");
$$ = 0;
}
| '~' '|' expr_primary %prec UNARY_PREC
{ yyerror(@1, "error: '~' '|' is not a valid expression. "
"Please use operator '~|' instead.");
$$ = 0;
}
| '~' '^' expr_primary %prec UNARY_PREC
{ yyerror(@1, "error: '~' '^' is not a valid expression. "
"Please use operator '~^' instead.");
$$ = 0;
}
More unary operators.
1999-06-13 19:30:23 +02:00
| K_NAND expr_primary %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('A', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
More unary operators.
1999-06-13 19:30:23 +02:00
$$ = tmp;
}
| K_NOR expr_primary %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('N', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
More unary operators.
1999-06-13 19:30:23 +02:00
$$ = tmp;
}
| K_NXOR expr_primary %prec UNARY_PREC
{ PEUnary*tmp = new PEUnary('X', $2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
More unary operators.
1999-06-13 19:30:23 +02:00
$$ = tmp;
}
Catch bad operand to some unary operators.
2000-04-21 05:22:18 +02:00
| '!' error %prec UNARY_PREC
{ yyerror(@1, "error: Operand of unary ! "
"is not a primary expression.");
$$ = 0;
}
| '^' error %prec UNARY_PREC
{ yyerror(@1, "error: Operand of reduction ^ "
"is not a primary expression.");
$$ = 0;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
| expression '^' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('^', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add support for power in constant expressions.
2006-07-31 05:50:17 +02:00
| expression K_POW expression
Rework shift and power PExpr nodes for their special needs. The power (**) and shift operators are different from other binary operators because their expression width calculations rely only on their left operand, with their right operand self-determined. Get the handling of these operators out of the PEBinary base class to prevent confusion.
2008-11-28 23:40:25 +01:00
{ PEBinary*tmp = new PEBPower('p', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Add support for power in constant expressions.
2006-07-31 05:50:17 +02:00
$$ = tmp;
}
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
| expression '*' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('*', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
| expression '/' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('/', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
| expression '%' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('%', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
| expression '+' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('+', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
| expression '-' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('-', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
| expression '&' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('&', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
| expression '|' expression
Line number information.
1999-05-27 05:31:29 +02:00
{ PEBinary*tmp = new PEBinary('|', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
}
Add support for binary nand operator.
2002-09-12 17:49:43 +02:00
| expression K_NAND expression
{ PEBinary*tmp = new PEBinary('A', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Add support for binary nand operator.
2002-09-12 17:49:43 +02:00
$$ = tmp;
}
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
| expression K_NOR expression
{ PEBinary*tmp = new PEBinary('O', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
$$ = tmp;
}
| expression K_NXOR expression
{ PEBinary*tmp = new PEBinary('X', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Elaborate ~^ and ~| operators.
1999-09-30 04:43:01 +02:00
$$ = tmp;
}
Parse more things.
1999-05-08 22:19:20 +02:00
| expression '<' expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('<', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Parse more things.
1999-05-08 22:19:20 +02:00
}
| expression '>' expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('>', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Parse more things.
1999-05-08 22:19:20 +02:00
}
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
| expression K_LS expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBShift('l', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
| expression K_RS expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBShift('r', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
Add arithmetic shift operators.
2003-06-18 05:55:18 +02:00
| expression K_RSS expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBShift('R', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Add arithmetic shift operators.
2003-06-18 05:55:18 +02:00
$$ = tmp;
}
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
| expression K_EQ expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('e', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
}
| expression K_CEQ expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('E', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
}
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
| expression K_LE expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('L', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
| expression K_GE expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('G', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Redo constant expression detection to happen after parsing. Parse more operators and expressions.
1999-05-16 07:08:42 +02:00
}
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
| expression K_NE expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('n', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
}
| expression K_CNE expression
Expression widths with unsized literals are pseudo-infinite width.
2006-10-30 06:44:49 +01:00
{ PEBinary*tmp = new PEBComp('N', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
}
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
| expression K_LOR expression
Elaborate logical and/or to account for special properties. The arguments of logical and/or are self determined, and the width is fixed as 1 bit. Account for this special behavior by creating the PEBLogic class.
2008-10-30 04:31:26 +01:00
{ PEBinary*tmp = new PEBLogic('o', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
}
| expression K_LAND expression
Elaborate logical and/or to account for special properties. The arguments of logical and/or are self determined, and the width is fixed as 1 bit. Account for this special behavior by creating the PEBLogic class.
2008-10-30 04:31:26 +01:00
{ PEBinary*tmp = new PEBLogic('a', $1, $3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Line number information.
1999-05-27 05:31:29 +02:00
$$ = tmp;
Support more operators, especially logical.
1999-03-15 03:43:32 +01:00
}
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
| expression '?' expression ':' expression
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
{ PETernary*tmp = new PETernary($1, $3, $5);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @2);
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
$$ = tmp;
Much expression parsing work, mark continuous assigns with source line info, replace some assertion failures with Sorry messages.
1999-05-20 06:31:45 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
Add min_typ_max to expressions. This patch adds min_typ_max to expressions. Remember when using a min_typ_max triplet in an expression they must be enclosed with parenthesis (1364-2001 section 4.3 page 58).
2007-09-16 17:25:03 +02:00
expr_mintypmax
: expression
{ $$ = $1; }
| expression ':' expression ':' expression
{ switch (min_typ_max_flag) {
case MIN:
$$ = $1;
delete $3;
delete $5;
break;
case TYP:
delete $1;
$$ = $3;
delete $5;
break;
case MAX:
delete $1;
delete $3;
$$ = $5;
break;
}
Make min/typ/max default warning message universal. The min/typ/max default warning was not being produced in all locations a min/typ/max expression could be used. This patch adds the default warning code to all locations. It also modifies the manual page to explicitly state that only the first ten warnings are printed.
2007-11-21 20:07:40 +01:00
if (min_typ_max_warn > 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << $$->get_fileline() << ": warning: choosing ";
Make min/typ/max default warning message universal. The min/typ/max default warning was not being produced in all locations a min/typ/max expression could be used. This patch adds the default warning code to all locations. It also modifies the manual page to explicitly state that only the first ten warnings are printed.
2007-11-21 20:07:40 +01:00
switch (min_typ_max_flag) {
case MIN:
cerr << "min";
break;
case TYP:
cerr << "typ";
break;
case MAX:
cerr << "max";
break;
}
cerr << " expression." << endl;
min_typ_max_warn -= 1;
}
Add min_typ_max to expressions. This patch adds min_typ_max to expressions. Remember when using a min_typ_max triplet in an expression they must be enclosed with parenthesis (1364-2001 section 4.3 page 58).
2007-09-16 17:25:03 +02:00
}
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
/* Many contexts take a comma separated list of expressions. Null
expressions can happen anywhere in the list, so there are two
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
extra rules in expression_list_with_nuls for parsing and
installing those nulls.
The expression_list_proper rules do not allow null items in the
expression list, so can be used where nul expressions are not allowed. */
expression_list_with_nuls
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
: expression_list_with_nuls ',' expression
{ list<PExpr*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
| expression
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($1);
$$ = tmp;
}
|
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back(0);
$$ = tmp;
}
| expression_list_with_nuls ','
{ list<PExpr*>*tmp = $1;
tmp->push_back(0);
$$ = tmp;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
expression_list_proper
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
: expression_list_proper ',' expression
{ list<PExpr*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
| expression
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($1);
$$ = tmp;
}
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
expr_primary
Support SystemVerilog size cast.
2011-09-19 04:21:46 +02:00
: number
{ assert($1);
PENumber*tmp = new PENumber($1);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| REALTIME
{ PEFNumber*tmp = new PEFNumber($1);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| STRING
{ PEString*tmp = new PEString($1);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| SYSTEM_IDENTIFIER
{ perm_string tn = lex_strings.make($1);
PECallFunction*tmp = new PECallFunction(tn);
FILE_NAME(tmp, @1);
$$ = tmp;
delete[]$1;
}
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
/* The hierarchy_identifier rule matches simple identifiers as well as
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
indexed arrays and part selects */
Add support for indexed select attached to parameters.
2005-10-04 06:09:25 +02:00
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ PEIdent*tmp = new PEIdent(*$1);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
$$ = tmp;
delete $1;
}
Add support for indexed select attached to parameters.
2005-10-04 06:09:25 +02:00
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
2008-01-29 21:19:59 +01:00
/* An identifier followed by an expression list in parentheses is a
Add support for indexed select attached to parameters.
2005-10-04 06:09:25 +02:00
function call. If a system identifier, then a system function
call. */
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
| hierarchy_identifier '(' expression_list_proper ')'
{ PECallFunction*tmp = new PECallFunction(*$1, *$3);
FILE_NAME(tmp, @1);
delete $1;
$$ = tmp;
}
| SYSTEM_IDENTIFIER '(' expression_list_proper ')'
{ perm_string tn = lex_strings.make($1);
PECallFunction*tmp = new PECallFunction(tn, *$3);
FILE_NAME(tmp, @1);
delete[]$1;
$$ = tmp;
}
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
| hierarchy_identifier '(' ')'
{ const vector<PExpr*> empty;
PECallFunction*tmp = new PECallFunction(*$1, empty);
FILE_NAME(tmp, @1);
delete $1;
$$ = tmp;
if (!gn_system_verilog()) {
yyerror(@1, "error: Empty function argument list requires SystemVerilog.");
Handle empty argument list to system function. (SystemVerilog)
2011-11-06 18:13:09 +01:00
}
}
| SYSTEM_IDENTIFIER '(' ')'
{ perm_string tn = lex_strings.make($1);
const vector<PExpr*>empty;
PECallFunction*tmp = new PECallFunction(tn, empty);
FILE_NAME(tmp, @1);
delete[]$1;
$$ = tmp;
if (!gn_system_verilog()) {
yyerror(@1, "error: Empty function argument list requires SystemVerilog.");
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
}
}
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
/* Many of the VAMS built-in functions are available as builtin
Spelling fixes No code changes.
2008-06-10 18:02:24 +02:00
functions with $system_function equivalents. */
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
| K_acos '(' expression ')'
{ perm_string tn = perm_string::literal("$acos");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_acosh '(' expression ')'
{ perm_string tn = perm_string::literal("$acosh");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_asin '(' expression ')'
{ perm_string tn = perm_string::literal("$asin");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_asinh '(' expression ')'
{ perm_string tn = perm_string::literal("$asinh");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_atan '(' expression ')'
{ perm_string tn = perm_string::literal("$atan");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_atanh '(' expression ')'
{ perm_string tn = perm_string::literal("$atanh");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_atan2 '(' expression ',' expression ')'
{ perm_string tn = perm_string::literal("$atan2");
PECallFunction*tmp = make_call_function(tn, $3, $5);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_ceil '(' expression ')'
{ perm_string tn = perm_string::literal("$ceil");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_cos '(' expression ')'
{ perm_string tn = perm_string::literal("$cos");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_cosh '(' expression ')'
{ perm_string tn = perm_string::literal("$cosh");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_exp '(' expression ')'
{ perm_string tn = perm_string::literal("$exp");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_floor '(' expression ')'
{ perm_string tn = perm_string::literal("$floor");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_hypot '(' expression ',' expression ')'
{ perm_string tn = perm_string::literal("$hypot");
PECallFunction*tmp = make_call_function(tn, $3, $5);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_ln '(' expression ')'
{ perm_string tn = perm_string::literal("$ln");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_log '(' expression ')'
Rename $log to $log10. Verilog-2005 defines the base-10 log function to be $log10. This makes sense because in C the log() function is the natural log. So add the $log10 function. Since there may be legacy code that uses the $log function, leave it defined, but we should consider at least printing a warning when the $log function is used.
2008-05-04 03:29:52 +02:00
{ perm_string tn = perm_string::literal("$log10");
Handle Traditional Verilog-A math functions Verilog-AMS recommends that users use the system-function style math functions, but supports traditional style math functions for portability. Add the keywords and parse the traditional Verilog-A functions, and handle them as calls to the equivilent system function.
2008-05-04 03:05:51 +02:00
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_pow '(' expression ',' expression ')'
{ perm_string tn = perm_string::literal("$pow");
PECallFunction*tmp = make_call_function(tn, $3, $5);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_sin '(' expression ')'
{ perm_string tn = perm_string::literal("$sin");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_sinh '(' expression ')'
{ perm_string tn = perm_string::literal("$sinh");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_sqrt '(' expression ')'
{ perm_string tn = perm_string::literal("$sqrt");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_tan '(' expression ')'
{ perm_string tn = perm_string::literal("$tan");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_tanh '(' expression ')'
{ perm_string tn = perm_string::literal("$tanh");
PECallFunction*tmp = make_call_function(tn, $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
Add support for indexed select attached to parameters.
2005-10-04 06:09:25 +02:00
Implement abs/min/max operators for real values. Implement in behavioral the abs/min/max operators for real values. The parser treats these builtin functions as operators, unary or binary, and elaborates them appropriately. Also add enough code generator support to handle real valued expressions in thread context.
2008-05-04 06:54:42 +02:00
/* These mathematical functions are conveniently expressed as unary
and binary expressions. They behave much like unary/binary
operators, even though they are parsed as functions. */
| K_abs '(' expression ')'
{ PEUnary*tmp = new PEUnary('m', $3);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_max '(' expression ',' expression ')'
{ PEBinary*tmp = new PEBinary('M', $3, $5);
FILE_NAME(tmp,@1);
$$ = tmp;
}
| K_min '(' expression ',' expression ')'
{ PEBinary*tmp = new PEBinary('m', $3, $5);
FILE_NAME(tmp,@1);
$$ = tmp;
}
Add support for indexed select attached to parameters.
2005-10-04 06:09:25 +02:00
/* Parenthesized expressions are primaries. */
Support SystemVerilog size cast.
2011-09-19 04:21:46 +02:00
| '(' expr_mintypmax ')'
{ $$ = $2; }
Add support for indexed select attached to parameters.
2005-10-04 06:09:25 +02:00
/* Various kinds of concatenation expressions. */
Support SystemVerilog size cast.
2011-09-19 04:21:46 +02:00
| '{' expression_list_proper '}'
{ PEConcat*tmp = new PEConcat(*$2);
FILE_NAME(tmp, @1);
delete $2;
$$ = tmp;
}
| '{' expression '{' expression_list_proper '}' '}'
{ PExpr*rep = $2;
PEConcat*tmp = new PEConcat(*$4, rep);
FILE_NAME(tmp, @1);
delete $4;
$$ = tmp;
}
| '{' expression '{' expression_list_proper '}' error '}'
{ PExpr*rep = $2;
PEConcat*tmp = new PEConcat(*$4, rep);
FILE_NAME(tmp, @1);
delete $4;
$$ = tmp;
yyerror(@5, "error: Syntax error between internal '}' "
"and closing '}' of repeat concatenation.");
yyerrok;
}
/* Cast expressions are primaries */
| DEC_NUMBER '\'' '(' expression ')'
{ PExpr*base = $4;
if (gn_system_verilog()) {
PECastSize*tmp = new PECastSize($1->as_ulong(), base);
FILE_NAME(tmp, @1);
delete $1;
$$ = tmp;
} else {
yyerror(@1, "error: Size cast requires SystemVerilog.");
$$ = base;
}
}
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
/* Aggregate literals are primaries. */
| assignment_pattern
{ $$ = $1; }
Support SystemVerilog size cast.
2011-09-19 04:21:46 +02:00
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
/* A function_item_list borrows the task_port_item run to match
declarations of ports. We check later to make sure there are no
output or inout ports actually used. */
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
function_item_list
: function_item
Add functions up to elaboration (Ed Carter)
1999-07-31 21:14:47 +02:00
{ $$ = $1; }
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
| function_item_list function_item
Handle null returns from function_item
1999-09-30 02:48:04 +02:00
{ if ($1 && $2) {
svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
delete $1;
delete $2;
$$ = tmp;
} else if ($1) {
$$ = $1;
} else {
$$ = $2;
}
Add functions up to elaboration (Ed Carter)
1999-07-31 21:14:47 +02:00
}
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
;
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
function_item
: task_port_item
{ $$ = $1; }
| block_item_decl
{ $$ = 0; }
;
Parse more things.
1999-05-08 22:19:20 +02:00
/* A gate_instance is a module instantiation or a built in part
type. In any case, the gate has a set of connections to ports. */
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
gate_instance
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
: IDENTIFIER '(' expression_list_with_nuls ')'
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{ lgate*tmp = new lgate;
Get gat names, instead of the first character.
1999-08-02 01:25:51 +02:00
tmp->name = $1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
tmp->parms = $3;
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
tmp->file = @1.text;
tmp->lineno = @1.first_line;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = tmp;
}
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| IDENTIFIER range '(' expression_list_with_nuls ')'
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
{ lgate*tmp = new lgate;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*rng = $2;
Get gat names, instead of the first character.
1999-08-02 01:25:51 +02:00
tmp->name = $1;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
tmp->parms = $4;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
tmp->range[0] = rng->front(); rng->pop_front();
tmp->range[1] = rng->front(); rng->pop_front();
assert(rng->empty());
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
tmp->file = @1.text;
tmp->lineno = @1.first_line;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Elaborate gate ranges.
1999-02-15 03:06:15 +01:00
delete rng;
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| '(' expression_list_with_nuls ')'
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
{ lgate*tmp = new lgate;
tmp->name = "";
tmp->parms = $2;
Add the LineInfo class to carry the source file location of things. PGate, Statement and PProcess. elaborate handles module parameter mismatches, missing or incorrect lvalues for procedural assignment, and errors are propogated to the top of the elaboration call tree. Attach line numbers to processes, gates and assignment statements.
1999-01-25 06:45:56 +01:00
tmp->file = @1.text;
tmp->lineno = @1.first_line;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = tmp;
}
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
Handle instance array of port-less modules.
2004-09-05 20:09:47 +02:00
/* Degenerate modules can have no ports. */
| IDENTIFIER range
{ lgate*tmp = new lgate;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*rng = $2;
Handle instance array of port-less modules.
2004-09-05 20:09:47 +02:00
tmp->name = $1;
tmp->parms = 0;
Parse the case of module arrays with port binding by name.
2006-12-06 06:32:36 +01:00
tmp->parms_by_name = 0;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
tmp->range[0] = rng->front(); rng->pop_front();
tmp->range[1] = rng->front(); rng->pop_front();
assert(rng->empty());
Handle instance array of port-less modules.
2004-09-05 20:09:47 +02:00
tmp->file = @1.text;
tmp->lineno = @1.first_line;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Handle instance array of port-less modules.
2004-09-05 20:09:47 +02:00
delete rng;
$$ = tmp;
}
Better parsing of expressions lists will empty expressoins.
2000-05-23 18:03:13 +02:00
/* Modules can also take ports by port-name expressions. */
Parse more things.
1999-05-08 22:19:20 +02:00
| IDENTIFIER '(' port_name_list ')'
{ lgate*tmp = new lgate;
Get gat names, instead of the first character.
1999-08-02 01:25:51 +02:00
tmp->name = $1;
Parse the case of module arrays with port binding by name.
2006-12-06 06:32:36 +01:00
tmp->parms = 0;
module parameter bind by name.
1999-05-29 04:36:17 +02:00
tmp->parms_by_name = $3;
Parse more things.
1999-05-08 22:19:20 +02:00
tmp->file = @1.text;
tmp->lineno = @1.first_line;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Parse more things.
1999-05-08 22:19:20 +02:00
$$ = tmp;
}
Parse the case of module arrays with port binding by name.
2006-12-06 06:32:36 +01:00
| IDENTIFIER range '(' port_name_list ')'
{ lgate*tmp = new lgate;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*rng = $2;
Parse the case of module arrays with port binding by name.
2006-12-06 06:32:36 +01:00
tmp->name = $1;
tmp->parms = 0;
tmp->parms_by_name = $4;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
tmp->range[0] = rng->front(); rng->pop_front();
tmp->range[1] = rng->front(); rng->pop_front();
assert(rng->empty());
Parse the case of module arrays with port binding by name.
2006-12-06 06:32:36 +01:00
tmp->file = @1.text;
tmp->lineno = @1.first_line;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Parse the case of module arrays with port binding by name.
2006-12-06 06:32:36 +01:00
delete rng;
$$ = tmp;
}
Print a better message for instance port expression errors. This patch adds code to print an error message when there is a syntax error in the port expression list.
2008-08-23 04:32:01 +02:00
| IDENTIFIER '(' error ')'
{ lgate*tmp = new lgate;
tmp->name = $1;
tmp->parms = 0;
tmp->parms_by_name = 0;
tmp->file = @1.text;
tmp->lineno = @1.first_line;
yyerror(@2, "error: Syntax error in instance port "
"expression(s).");
delete[]$1;
$$ = tmp;
}
| IDENTIFIER range '(' error ')'
{ lgate*tmp = new lgate;
tmp->name = $1;
tmp->parms = 0;
tmp->parms_by_name = 0;
tmp->file = @1.text;
tmp->lineno = @1.first_line;
yyerror(@3, "error: Syntax error in instance port "
"expression(s).");
delete[]$1;
$$ = tmp;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
gate_instance_list
: gate_instance_list ',' gate_instance
Get rid of list<lgate> types.
1999-05-06 06:37:17 +02:00
{ svector<lgate>*tmp1 = $1;
lgate*tmp2 = $3;
svector<lgate>*out = new svector<lgate> (*tmp1, *tmp2);
delete tmp1;
delete tmp2;
$$ = out;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
| gate_instance
Get rid of list<lgate> types.
1999-05-06 06:37:17 +02:00
{ svector<lgate>*tmp = new svector<lgate>(1);
(*tmp)[0] = *$1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
delete $1;
$$ = tmp;
}
;
gatetype
: K_and { $$ = PGBuiltin::AND; }
| K_nand { $$ = PGBuiltin::NAND; }
| K_or { $$ = PGBuiltin::OR; }
| K_nor { $$ = PGBuiltin::NOR; }
| K_xor { $$ = PGBuiltin::XOR; }
| K_xnor { $$ = PGBuiltin::XNOR; }
| K_buf { $$ = PGBuiltin::BUF; }
| K_bufif0 { $$ = PGBuiltin::BUFIF0; }
| K_bufif1 { $$ = PGBuiltin::BUFIF1; }
| K_not { $$ = PGBuiltin::NOT; }
| K_notif0 { $$ = PGBuiltin::NOTIF0; }
| K_notif1 { $$ = PGBuiltin::NOTIF1; }
The switch gates do not support a strength specification. This patch splits the switch types out of the gates to allow them to be defined to not take a strength specification.
2010-07-14 01:12:03 +02:00
;
switchtype
: K_nmos { $$ = PGBuiltin::NMOS; }
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
| K_rnmos { $$ = PGBuiltin::RNMOS; }
| K_pmos { $$ = PGBuiltin::PMOS; }
| K_rpmos { $$ = PGBuiltin::RPMOS; }
| K_cmos { $$ = PGBuiltin::CMOS; }
| K_rcmos { $$ = PGBuiltin::RCMOS; }
| K_tran { $$ = PGBuiltin::TRAN; }
| K_rtran { $$ = PGBuiltin::RTRAN; }
| K_tranif0 { $$ = PGBuiltin::TRANIF0; }
| K_tranif1 { $$ = PGBuiltin::TRANIF1; }
| K_rtranif0 { $$ = PGBuiltin::RTRANIF0; }
| K_rtranif1 { $$ = PGBuiltin::RTRANIF1; }
;
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
/* A general identifier is a hierarchical name, with the right most
name the base of the identifier. This rule builds up a
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
hierarchical name from the left to the right, forming a list of
names. */
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
hierarchy_identifier
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
: IDENTIFIER
{ $$ = new pform_name_t;
$$->push_back(name_component_t(lex_strings.make($1)));
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '.' IDENTIFIER
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ pform_name_t * tmp = $1;
tmp->push_back(name_component_t(lex_strings.make($3)));
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$3;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
$$ = tmp;
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '[' expression ']'
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
itmp.sel = index_component_t::SEL_BIT;
itmp.msb = $3;
tail.index.push_back(itmp);
$$ = tmp;
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '[' expression ':' expression ']'
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
itmp.sel = index_component_t::SEL_PART;
itmp.msb = $3;
itmp.lsb = $5;
tail.index.push_back(itmp);
$$ = tmp;
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '[' expression K_PO_POS expression ']'
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
itmp.sel = index_component_t::SEL_IDX_UP;
itmp.msb = $3;
itmp.lsb = $5;
tail.index.push_back(itmp);
$$ = tmp;
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '[' expression K_PO_NEG expression ']'
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
itmp.sel = index_component_t::SEL_IDX_DO;
itmp.msb = $3;
itmp.lsb = $5;
tail.index.push_back(itmp);
$$ = tmp;
}
;
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
/* This is a list of identifiers. The result is a list of strings,
each one of the identifiers in the list. These are simple,
non-hierarchical names separated by ',' characters. */
list_of_identifiers
: IDENTIFIER
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
{ $$ = list_from_identifier($1); }
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
| list_of_identifiers ',' IDENTIFIER
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
{ $$ = list_from_identifier($1, $3); }
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
;
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
list_of_port_identifiers
: IDENTIFIER
{ $$ = make_port_list($1, 0); }
| IDENTIFIER '=' expression
{ $$ = make_port_list($1, $3); }
| list_of_port_identifiers ',' IDENTIFIER
{ $$ = make_port_list($1, $3, 0); }
| list_of_port_identifiers ',' IDENTIFIER '=' expression
{ $$ = make_port_list($1, $3, $5); }
;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
/* The list_of_ports and list_of_port_declarations rules are the
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
port list formats for module ports. The list_of_ports_opt rule is
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
only used by the module start rule.
The first, the list_of_ports, is the 1364-1995 format, a list of
port names, including .name() syntax.
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
The list_of_port_declarations the 1364-2001 format, an in-line
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
declaration of the ports.
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
In both cases, the list_of_ports and list_of_port_declarations
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
returns an array of Module::port_t* items that include the name
of the port internally and externally. The actual creation of the
nets/variables is done in the declaration, whether internal to
the port list or in amongst the module items. */
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
list_of_ports
Handle unconnected module ports.
1999-09-17 04:06:25 +02:00
: port_opt
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
{ vector<Module::port_t*>*tmp
= new vector<Module::port_t*>(1);
parse more verilog.
1999-06-12 22:35:27 +02:00
(*tmp)[0] = $1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = tmp;
}
Handle unconnected module ports.
1999-09-17 04:06:25 +02:00
| list_of_ports ',' port_opt
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
{ vector<Module::port_t*>*tmp = $1;
tmp->push_back($3);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = tmp;
}
;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
list_of_port_declarations
: port_declaration
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
{ vector<Module::port_t*>*tmp
= new vector<Module::port_t*>(1);
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
(*tmp)[0] = $1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = tmp;
}
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
| list_of_port_declarations ',' port_declaration
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
{ vector<Module::port_t*>*tmp = $1;
tmp->push_back($3);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = tmp;
}
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
| list_of_port_declarations ',' IDENTIFIER
{ Module::port_t*ptmp;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
perm_string name = lex_strings.make($3);
ptmp = pform_module_port_reference(name, @3.text,
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
@3.first_line);
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
vector<Module::port_t*>*tmp = $1;
tmp->push_back(ptmp);
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
/* Get the port declaration details, the port type
and what not, from context data stored by the
last port_declaration rule. */
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
pform_module_define_port(@3, name,
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
port_declaration_context.port_type,
port_declaration_context.port_net_type,
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.var_type,
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
port_declaration_context.sign_flag,
Allow attributes on Verilog 2001 port declarations.
2003-07-04 05:57:18 +02:00
port_declaration_context.range, 0);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$3;
Ansi port declaration can take a list.
2003-04-25 04:28:53 +02:00
$$ = tmp;
Fix handling of inline decloration without wire keyword.
2003-02-08 00:16:09 +01:00
}
Add better error reporting for port declarations. Add an error message for NULL port declarations and for a ';' that could be left over from building a port declaration from an old style declaration.
2007-12-29 08:47:20 +01:00
| list_of_port_declarations ','
{
yyerror(@2, "error: NULL port declarations are not "
"allowed.");
}
| list_of_port_declarations ';'
{
yyerror(@2, "error: ';' is an invalid port declaration "
"separator.");
}
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
;
port_declaration
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
: attribute_list_opt
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
K_input net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ Module::port_t*ptmp;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
perm_string name = lex_strings.make($7);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::PINPUT,
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
$3, $4, $5, $6, $1);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
port_declaration_context.port_type = NetNet::PINPUT;
port_declaration_context.port_net_type = $3;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.var_type = $4;
port_declaration_context.sign_flag = $5;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
delete port_declaration_context.range;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.range = $6;
delete[]$7;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = ptmp;
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
| attribute_list_opt
K_input atom2_type signed_unsigned_opt IDENTIFIER
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($5);
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*use_range = make_range_from_width($3);
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::PINPUT,
NetNet::UNRESOLVED_WIRE, IVL_VT_BOOL,
Give module port atom2 objects their proper widths. These widths can be expressions as ranges, but must be present as this is how we identify them as the various types of ints.
2010-10-20 04:07:44 +02:00
$4, use_range, $1);
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
port_declaration_context.port_type = NetNet::PINPUT;
port_declaration_context.port_net_type = NetNet::UNRESOLVED_WIRE;
port_declaration_context.var_type = IVL_VT_BOOL;
port_declaration_context.sign_flag = $4;
delete port_declaration_context.range;
Give module port atom2 objects their proper widths. These widths can be expressions as ranges, but must be present as this is how we identify them as the various types of ints.
2010-10-20 04:07:44 +02:00
port_declaration_context.range = use_range;
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
delete[]$5;
$$ = ptmp;
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
| attribute_list_opt
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
K_input K_wreal IDENTIFIER
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($4);
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::PINPUT,
NetNet::WIRE, IVL_VT_REAL, true, 0, $1);
port_declaration_context.port_type = NetNet::PINPUT;
port_declaration_context.port_net_type = NetNet::WIRE;
port_declaration_context.var_type = IVL_VT_REAL;
port_declaration_context.sign_flag = true;
delete port_declaration_context.range;
port_declaration_context.range = 0;
delete[]$4;
$$ = ptmp;
}
| attribute_list_opt
K_inout net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ Module::port_t*ptmp;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
perm_string name = lex_strings.make($7);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::PINOUT,
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
$3, $4, $5, $6, $1);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
port_declaration_context.port_type = NetNet::PINOUT;
port_declaration_context.port_net_type = $3;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.var_type = $4;
port_declaration_context.sign_flag = $5;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
delete port_declaration_context.range;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.range = $6;
delete[]$7;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = ptmp;
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
| attribute_list_opt
K_inout K_wreal IDENTIFIER
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($4);
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::PINOUT,
NetNet::WIRE, IVL_VT_REAL, true, 0, $1);
port_declaration_context.port_type = NetNet::PINOUT;
port_declaration_context.port_net_type = NetNet::WIRE;
port_declaration_context.var_type = IVL_VT_REAL;
port_declaration_context.sign_flag = true;
delete port_declaration_context.range;
port_declaration_context.range = 0;
delete[]$4;
$$ = ptmp;
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
| attribute_list_opt
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
K_output net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ Module::port_t*ptmp;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
perm_string name = lex_strings.make($7);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
Revert "Assume module output primitive arguments as variables by default" This reverts commit 537b8cba34443f5d1e4a4a168122bcf5e8173a50. Whatever problem that report was trying to address was addressed wrongly by the reverted patch.
2011-11-26 02:18:27 +01:00
$3, $4, $5, $6, $1);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
port_declaration_context.port_type = NetNet::POUTPUT;
Revert "Assume module output primitive arguments as variables by default" This reverts commit 537b8cba34443f5d1e4a4a168122bcf5e8173a50. Whatever problem that report was trying to address was addressed wrongly by the reverted patch.
2011-11-26 02:18:27 +01:00
port_declaration_context.port_net_type = $3;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.var_type = $4;
port_declaration_context.sign_flag = $5;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
delete port_declaration_context.range;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.range = $6;
delete[]$7;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = ptmp;
}
| attribute_list_opt
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
K_output var_type primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ Module::port_t*ptmp;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
perm_string name = lex_strings.make($7);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
$3, $4, $5, $6, $1);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = $3;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.var_type = $4;
port_declaration_context.sign_flag = $5;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
delete port_declaration_context.range;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.range = $6;
delete[]$7;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = ptmp;
}
| attribute_list_opt
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
K_output var_type primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER '=' expression
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ Module::port_t*ptmp;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
perm_string name = lex_strings.make($7);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
$3, $4, $5, $6, $1);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = $3;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.var_type = $4;
port_declaration_context.sign_flag = $5;
Allow multiple ports in single ANSI decl for tasks and functions This patch adds the functionality to tasks/functions to handle the declaration of multiple ports using a single ANSI declaration. It also deletes the old range vector before it adds the new one. The tasks and functions are different than modules so we need to copy the range for them.
2008-04-25 22:48:14 +02:00
delete port_declaration_context.range;
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
port_declaration_context.range = $6;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
pform_make_reginit(@7, name, $9);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
Initialization of bit/logic in module declaration The module declaration should allow initialization of the bit and logic data types. For example: $ cat clkgen.sv module clkgen(output logic clk = 0, output bit p = 1); initial begin #200; $display("p = %b", p); $finish; end initial forever #10 clk = ~clk; endmodule $ iverilog -g 2009 clkgen.sv $ ./a.out p = 1 Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-11 18:26:45 +02:00
delete[]$7;
$$ = ptmp;
}
| attribute_list_opt
K_output net_type_opt primitive_type_opt unsigned_signed_opt range_opt IDENTIFIER '=' expression
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($7);
Revert "Assume module output primitive arguments as variables by default" This reverts commit 537b8cba34443f5d1e4a4a168122bcf5e8173a50. Whatever problem that report was trying to address was addressed wrongly by the reverted patch.
2011-11-26 02:18:27 +01:00
NetNet::Type t = ($3 == NetNet::IMPLICIT) ? NetNet::IMPLICIT_REG : $3;
Initialization of bit/logic in module declaration The module declaration should allow initialization of the bit and logic data types. For example: $ cat clkgen.sv module clkgen(output logic clk = 0, output bit p = 1); initial begin #200; $display("p = %b", p); $finish; end initial forever #10 clk = ~clk; endmodule $ iverilog -g 2009 clkgen.sv $ ./a.out p = 1 Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-11 18:26:45 +02:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
t, $4, $5, $6, $1);
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = t;
port_declaration_context.var_type = $4;
port_declaration_context.sign_flag = $5;
delete port_declaration_context.range;
port_declaration_context.range = $6;
pform_make_reginit(@7, name, $9);
Add support for primitive types of ports. The infrastructure is already there, all that's missing is the syntax in the parser.
2010-03-11 21:22:41 +01:00
delete[]$7;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = ptmp;
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
| attribute_list_opt
K_output atom2_type signed_unsigned_opt IDENTIFIER
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($5);
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
list<PExpr*>*use_range = make_range_from_width($3);
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
NetNet::IMPLICIT_REG, IVL_VT_BOOL,
Give module port atom2 objects their proper widths. These widths can be expressions as ranges, but must be present as this is how we identify them as the various types of ints.
2010-10-20 04:07:44 +02:00
$4, use_range, $1);
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = NetNet::IMPLICIT_REG;
port_declaration_context.var_type = IVL_VT_BOOL;
port_declaration_context.sign_flag = $4;
delete port_declaration_context.range;
Give module port atom2 objects their proper widths. These widths can be expressions as ranges, but must be present as this is how we identify them as the various types of ints.
2010-10-20 04:07:44 +02:00
port_declaration_context.range = use_range;
Handle atom2 types in modules input/output ports.
2010-10-19 04:23:02 +02:00
delete[]$5;
$$ = ptmp;
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
| attribute_list_opt
K_output atom2_type signed_unsigned_opt IDENTIFIER '=' expression
Initialization of atom types in module declaration The module declaration should allow initialization of atom types (byte, short int, int, and longint) data types. For example: $ cat clkgen.sv module clkgen(output logic clk = 0, output byte p = '1); initial begin #200; $display("p = %b", p); $finish; end initial forever #10 clk = ~clk; endmodule $ iverilog -g 2009 clkgen.sv $ ./a.out p = 11111111 $ Suggested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-11 19:15:39 +02:00
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($5);
list<PExpr*>*use_range = make_range_from_width($3);
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
NetNet::IMPLICIT_REG, IVL_VT_BOOL,
$4, use_range, $1);
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = NetNet::IMPLICIT_REG;
port_declaration_context.var_type = IVL_VT_BOOL;
port_declaration_context.sign_flag = $4;
delete port_declaration_context.range;
port_declaration_context.range = use_range;
pform_make_reginit(@5, name, $7);
delete[]$5;
$$ = ptmp;
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
| attribute_list_opt
K_output K_wreal IDENTIFIER
{ Module::port_t*ptmp;
perm_string name = lex_strings.make($4);
ptmp = pform_module_port_reference(name, @2.text,
@2.first_line);
pform_module_define_port(@2, name, NetNet::POUTPUT,
NetNet::WIRE, IVL_VT_REAL, true, 0, $1);
port_declaration_context.port_type = NetNet::POUTPUT;
port_declaration_context.port_net_type = NetNet::WIRE;
port_declaration_context.var_type = IVL_VT_REAL;
port_declaration_context.sign_flag = true;
delete port_declaration_context.range;
port_declaration_context.range = 0;
delete[]$4;
$$ = ptmp;
}
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Fix handling of inline decloration without wire keyword.
2003-02-08 00:16:09 +01:00
net_type_opt
: net_type { $$ = $1; }
| { $$ = NetNet::IMPLICIT; }
;
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
/*
* The signed_opt rule will return "true" if K_signed is present,
* for "false" otherwise. This rule corresponds to the declaration
* defaults for reg/bit/logic.
*
* The signed_unsigned_opt rule with match K_signed or K_unsigned
* and return true or false as appropriate. The default is
* "true". This corresponds to the declaration defaults for
* byte/shortint/int/longint.
*/
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
unsigned_signed_opt
: K_signed { $$ = true; }
| K_unsigned { $$ = false; }
| { $$ = false; }
Parse support for SystemVerilog atom2 types.
2010-10-02 19:13:11 +02:00
;
signed_unsigned_opt
: K_signed { $$ = true; }
| K_unsigned { $$ = false; }
| { $$ = true; }
;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
/*
* In some places we can take any of the 4 2-value atom-type
* names. All the context needs to know if that type is its width.
*/
atom2_type
: K_byte { $$ = 8; }
| K_shortint { $$ = 16; }
| K_int { $$ = 32; }
| K_longint { $$ = 64; }
;
Parse more complex continuous assign lvalues.
1999-05-07 06:26:49 +02:00
/* An lpvalue is the expression that can go on the left side of a
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
procedural assignment. This rule handles only procedural
Spelling fixes Mostly then/than confusion. All comments or README files, except for one user-visible change in a tgt-vlog95 error message.
2011-03-11 20:27:54 +01:00
assignments. It is more limited than the general expr_primary
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
rule to reflect the rules for assignment l-values. */
Parse more complex continuous assign lvalues.
1999-05-07 06:26:49 +02:00
lpvalue
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
: hierarchy_identifier
{ PEIdent*tmp = new PEIdent(*$1);
FILE_NAME(tmp, @1);
$$ = tmp;
delete $1;
}
| implicit_class_handle '.' hierarchy_identifier
{ yyerror(@1, "sorry: implicit class handles (this/super) not supported.");
PEIdent*tmp = new PEIdent(*$3);
FILE_NAME(tmp, @1);
$$ = tmp;
delete $3;
}
| '{' expression_list_proper '}'
{ PEConcat*tmp = new PEConcat(*$2);
FILE_NAME(tmp, @1);
delete $2;
$$ = tmp;
}
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Rename assign_list to cont_assign_list.
2007-04-21 06:45:36 +02:00
/* Continuous assignments have a list of individual assignments. */
cont_assign
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
: lpvalue '=' expression
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($1);
tmp->push_back($3);
$$ = tmp;
}
;
continuous assignment lists.
1999-08-27 17:08:37 +02:00
Rename assign_list to cont_assign_list.
2007-04-21 06:45:36 +02:00
cont_assign_list
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
: cont_assign_list ',' cont_assign
{ list<PExpr*>*tmp = $1;
tmp->splice(tmp->end(), *$3);
delete $3;
$$ = tmp;
}
| cont_assign
{ $$ = $1; }
;
continuous assignment lists.
1999-08-27 17:08:37 +02:00
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
/* We allow zero, one or two unique declarations. */
local_timeunit_prec_decl_opt
: /* Empty */
| local_timeunit_prec_decl
| local_timeunit_prec_decl local_timeunit_prec_decl
;
/* By setting the appropriate have_time???_decl we allow only
one declaration of each type in this module. */
local_timeunit_prec_decl
: K_timeunit TIME_LITERAL ';'
{ pform_set_timeunit($2, true, false);
have_timeunit_decl = true;
}
| K_timeprecision TIME_LITERAL ';'
{ pform_set_timeprecision($2, true, false);
have_timeprec_decl = true;
}
;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
/* This is the global structure of a module. A module in a start
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
section, with optional ports, then an optional list of module
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
items, and finally an end marker. */
Parse program blocks / Fix module end-name syntax.
2012-02-18 19:02:54 +01:00
module
: attribute_list_opt module_start IDENTIFIER
{ pform_startmodule($3, @2.text, @2.first_line, $1); }
module_parameter_port_list_opt
module_port_list_opt
module_attribute_foreign ';'
{ pform_module_set_ports($6); }
local_timeunit_prec_decl_opt
{ have_timeunit_decl = true; // Every thing past here is
have_timeprec_decl = true; // a check!
pform_check_timeunit_prec();
}
module_item_list_opt
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
module_end
Parse program blocks / Fix module end-name syntax.
2012-02-18 19:02:54 +01:00
{ Module::UCDriveType ucd;
// The lexor detected `unconnected_drive directives and
// marked what it found in the uc_drive variable. Use that
// to generate a UCD flag for the module.
switch (uc_drive) {
case UCD_NONE:
default:
ucd = Module::UCD_NONE;
break;
case UCD_PULL0:
ucd = Module::UCD_PULL0;
break;
case UCD_PULL1:
ucd = Module::UCD_PULL1;
break;
}
// Check that program/endprogram and module/endmodule
// keywords match.
if ($2 != $13) {
switch ($2) {
case K_module:
yyerror(@13, "error: module not closed by endmodule.");
break;
case K_program:
yyerror(@13, "error: program not closed by endprogram.");
break;
default:
break;
}
}
if ($2 == K_program) {
yyerror(@2, "sorry: Program blocks not supported yet.");
}
pform_endmodule($3, in_celldefine, ucd);
delete[]$3;
have_timeunit_decl = false; // We will allow decls again.
have_timeprec_decl = false;
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
endname_opt
{ // Last step: check any closing name. This is done late so
// that the parser can look ahead to detect the present
// endname_opt but still have the pform_endmodule() called
// early enough that the lexor can know we are outside the
// module.
if ($15 && (strcmp($3,$15) != 0)) {
yyerror(@15, "error: End name doesn't match module/program name");
}
if ($15) delete[]$15;
}
Parse program blocks / Fix module end-name syntax.
2012-02-18 19:02:54 +01:00
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse program blocks / Fix module end-name syntax.
2012-02-18 19:02:54 +01:00
/* Modules start with module/macromodule or program keyword, and end
with the endmodule or endprogram keyword. The syntax for modules
and programs is almost identical, so let semantics sort out the
differences. */
module_start
: K_module { $$ = K_module; }
| K_macromodule { $$ = K_module; }
| K_program { $$ = K_program; }
;
module_end
: K_endmodule { $$ = K_module; }
| K_endprogram { $$ = K_program; }
;
endname_opt
: ':' IDENTIFIER { $$ = $2; }
| { $$ = 0; }
;
Support macromodule as module.
2001-06-23 02:31:06 +02:00
Blind support for "integer foreign" attributes. (Stefan Theide) Allows iverilog to parse attribute like syntax that a common simuator puts into automatically generated verilog code. This syntax cannot be found in any of the IEEE standards.
2009-02-24 01:37:34 +01:00
module_attribute_foreign
: K_PSTAR IDENTIFIER K_integer IDENTIFIER '=' STRING ';' K_STARP { $$ = 0; }
| { $$ = 0; }
;
Add support for initialization assign in port list declaration of reg.
2004-01-21 04:37:12 +01:00
module_port_list_opt
: '(' list_of_ports ')' { $$ = $2; }
| '(' list_of_port_declarations ')' { $$ = $2; }
| { $$ = 0; }
;
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
2008-01-29 21:19:59 +01:00
/* Module declarations include optional ANSI style module parameter
Add ANSI style parameter port declarations.
2003-12-19 06:15:04 +01:00
ports. These are simply advance ways to declare parameters, so
that the port declarations may use them. */
module_parameter_port_list_opt
:
| '#' '(' module_parameter_port_list ')'
;
module_parameter_port_list
: K_parameter parameter_assign
| module_parameter_port_list ',' parameter_assign
| module_parameter_port_list ',' K_parameter parameter_assign
;
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
module_item
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
/* This rule detects net declarations that possibly include a
primitive type, an optional vector range and signed flag. This
also includes an optional delay set. The values are then applied
to a list of names. If the primitive type is not specified, then
resort to the default type LOGIC. */
: attribute_list_opt net_type
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
primitive_type_opt unsigned_signed_opt range_opt
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
delay3_opt
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
net_variable_list ';'
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
{ ivl_variable_type_t dtype = $3;
if (dtype == IVL_VT_NO_TYPE)
dtype = IVL_VT_LOGIC;
pform_makewire(@2, $5, $4, $7, $2,
NetNet::NOT_A_PORT, dtype, $1);
if ($6 != 0) {
yyerror(@6, "sorry: net delays not supported.");
delete $6;
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
delete $1;
}
| attribute_list_opt K_wreal delay3 net_variable_list ';'
{ pform_makewire(@2, 0, true, $4, NetNet::WIRE,
NetNet::NOT_A_PORT, IVL_VT_REAL, $1);
if ($3 != 0) {
yyerror(@3, "sorry: net delays not supported.");
delete $3;
}
delete $1;
}
| attribute_list_opt K_wreal net_variable_list ';'
{ pform_makewire(@2, 0, true, $3, NetNet::WIRE,
NetNet::NOT_A_PORT, IVL_VT_REAL, $1);
delete $1;
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
/* Very similar to the rule above, but this takes a list of
net_decl_assigns, which are <name> = <expr> assignment
declarations. */
| attribute_list_opt net_type
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
primitive_type_opt unsigned_signed_opt range_opt
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
delay3_opt net_decl_assigns ';'
{ ivl_variable_type_t dtype = $3;
if (dtype == IVL_VT_NO_TYPE)
dtype = IVL_VT_LOGIC;
pform_makewire(@2, $5, $4, $6,
str_strength, $7, $2, dtype);
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
if ($1) {
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
yyerror(@2, "sorry: Attributes not supported "
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
"on net declaration assignments.");
delete $1;
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Handle nets that are packed structures.
2011-12-18 21:00:18 +01:00
/* Allow struct nets. */
| attribute_list_opt net_type struct_data_type net_variable_list ';'
{ pform_makewire(@2, $3, NetNet::NOT_A_PORT, $4, $1);
delete $1;
}
| attribute_list_opt net_type struct_data_type error ';'
{ yyerror(@5, "error: Errors in net variable list.");
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
/* This form doesn't have the range, but does have strengths. This
gives strength to the assignment drivers. */
| attribute_list_opt net_type
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
primitive_type_opt unsigned_signed_opt
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
drive_strength net_decl_assigns ';'
{ ivl_variable_type_t dtype = $3;
if (dtype == IVL_VT_NO_TYPE)
dtype = IVL_VT_LOGIC;
pform_makewire(@2, 0, $4, 0, $5, $6, $2, dtype);
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
if ($1) {
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
yyerror(@2, "sorry: Attributes not supported "
Verilog 2001 attriubtes on nets/wires.
2002-05-24 06:36:23 +02:00
"on net declaration assignments.");
delete $1;
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
}
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
| attribute_list_opt K_wreal net_decl_assigns ';'
{ pform_makewire(@2, 0, true, 0, str_strength, $3,
NetNet::WIRE, IVL_VT_REAL);
if ($1) {
yyerror(@2, "sorry: Attributes not supported "
"on net declaration assignments.");
delete $1;
}
}
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
| K_trireg charge_strength_opt range_opt delay3_opt list_of_identifiers ';'
Standardize error/sorry messages.
1999-09-29 23:16:32 +02:00
{ yyerror(@1, "sorry: trireg nets not supported.");
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
delete $3;
delete $4;
Add lexical support for real numbers.
1999-06-15 04:50:02 +02:00
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction unsigned_signed_opt range_opt delay3_opt list_of_identifiers ';'
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
{ pform_set_port_type(@1, $5, $3, $2, $1);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
/* The next two rules handle Verilog 2001 statements of the form:
input wire signed [h:l] <list>;
This creates the wire and sets the port type all at once. */
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction net_type unsigned_signed_opt range_opt list_of_identifiers ';'
Fix range handling/checking and add a flag to allow deprecated port syntax. This patch is rather large and fixes a couple of problems. The major change is that instead of keeping all the range specifications in a list that is later processed the information is now kept as individual entries for the port and net definitions. This allows easier checking for multiple definitions (pr1660028), more detailed error messages and the ability to pass the now deprecated style of a scalar I/O definition used with a vectored net definition. These changes did require extra code to prevent a single definition from setting the range values in more than on place. When using the new ANSI-C style of port declarations (1364-2001 12.3.4 list_of_port_declarations) the compiler ensures that you do not redeclare the port in the body (it is already completely defined). This caught a few errors in the test suite (pr859 and sqrt32*). The flag to disable the normal port checking and allow the deprecated port syntax is -gno-io-range-error. This will print a warning for the case of a scalar port with a vectored definition in the body. All other cases are still considered an error.
2007-08-22 04:52:42 +02:00
{ pform_makewire(@1, $4, $3, $5, $2, $1, IVL_VT_NO_TYPE, 0,
SR_BOTH);
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
}
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
| K_output var_type unsigned_signed_opt range_opt list_of_port_identifiers ';'
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
{ list<pair<perm_string,PExpr*> >::const_iterator pp;
list<perm_string>*tmp = new list<perm_string>;
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
for (pp = $5->begin(); pp != $5->end(); ++ pp ) {
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
tmp->push_back((*pp).first);
}
pform_makewire(@1, $4, $3, tmp, $2, NetNet::POUTPUT,
IVL_VT_NO_TYPE, 0, SR_BOTH);
Change iterators to use prefix ++ since it is more efficient. This patch changes all the iterator code to use a prefix ++ instead of postfix since it is more efficient (no need for a temporary). It is likely that the compiler could optimize this away, but lets make it efficient from the start.
2010-10-23 23:57:59 +02:00
for (pp = $5->begin(); pp != $5->end(); ++ pp ) {
Add support for initializing outputs declared as output reg. The standard allows an output declared as "output reg" to be given an initialization assignment in the output declaration. this patch adds that functionality. Specifically: output reg out = 1'b0; works as expected.
2009-05-14 18:32:15 +02:00
if ((*pp).second) {
pform_make_reginit(@1, (*pp).first, (*pp).second);
}
}
delete $5;
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction K_wreal list_of_identifiers ';'
Add preliminary support for wreal in Verilog-AMS mode. This patch adds wreal support when in Verilog-AMS mode. It doesn't add everything that is shown in the Verilog-A standard. It adds the following: Declaring a wreal net. Declaring a wreal net with an initialization. Declaring a wreal input/output using ANSI syntax. Declaring a wreal input/output using the old style. Declaring wreal inout ports are also allowed and parsed, but the compiler does not know how to handle this. There are other deviations from what is shown in the Verilog-A standard, but this should get most of the syntax people actually use.
2011-11-24 04:07:26 +01:00
{ pform_makewire(@1, 0, true, $3, NetNet::WIRE, $1,
IVL_VT_REAL, 0, SR_BOTH);
}
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
/* var_type declaration (reg variables) cannot be input or output,
because the port declaration implies an external driver, which
cannot be attached to a reg. These rules catch that error early. */
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
| K_input var_type unsigned_signed_opt range_opt list_of_identifiers ';'
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
{ pform_makewire(@1, $4, $3, $5, $2, NetNet::PINPUT,
IVL_VT_NO_TYPE, 0);
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
yyerror(@2, "error: reg variables cannot be inputs.");
}
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
| K_inout var_type unsigned_signed_opt range_opt list_of_identifiers ';'
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
{ pform_makewire(@1, $4, $3, $5, $2, NetNet::PINOUT,
IVL_VT_NO_TYPE, 0);
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
yyerror(@2, "error: reg variables cannot be inouts.");
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction unsigned_signed_opt range_opt delay3_opt error ';'
task/function ports can have types.
2006-03-30 07:22:34 +02:00
{ yyerror(@1, "error: Invalid variable list"
Error message for invalid variable list.
2000-09-13 18:32:26 +02:00
" in port declaration.");
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
if ($3) delete $3;
if ($4) delete $4;
Error message for invalid variable list.
2000-09-13 18:32:26 +02:00
yyerrok;
}
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
/* Maybe this is a discipline declaration? If so, then the lexor
will see the discipline name as an identifier. We match it to the
discipline or type name semantically. */
| DISCIPLINE_IDENTIFIER list_of_identifiers ';'
{ pform_attach_discipline(@1, $1, $2); }
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
/* block_item_decl rule is shared with task blocks and named
begin/end. */
Handle integers at task parameters.
1999-09-10 07:02:09 +02:00
| block_item_decl
More 2001 port declaration support.
2003-04-28 19:50:57 +02:00
/* */
More syntax parse with sorry stubs.
1999-06-16 05:13:29 +02:00
| K_defparam defparam_assign_list ';'
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/* Most gate types have an optional drive strength and optional
The switch gates do not support a strength specification. This patch splits the switch types out of the gates to allow them to be defined to not take a strength specification.
2010-07-14 01:12:03 +02:00
two/three-value delay. These rules handle the different cases.
We check that the actual number of delays is correct later. */
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
| attribute_list_opt gatetype gate_instance_list ';'
{ pform_makegates($2, str_strength, 0, $3, $1);
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
}
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
| attribute_list_opt gatetype delay3 gate_instance_list ';'
{ pform_makegates($2, str_strength, $3, $4, $1);
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
}
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
| attribute_list_opt gatetype drive_strength gate_instance_list ';'
{ pform_makegates($2, $3, 0, $4, $1);
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
}
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
| attribute_list_opt gatetype drive_strength delay3 gate_instance_list ';'
{ pform_makegates($2, $3, $4, $5, $1);
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
}
The switch gates do not support a strength specification. This patch splits the switch types out of the gates to allow them to be defined to not take a strength specification.
2010-07-14 01:12:03 +02:00
/* The switch type gates do not support a strength. */
| attribute_list_opt switchtype gate_instance_list ';'
{ pform_makegates($2, str_strength, 0, $3, $1);
}
| attribute_list_opt switchtype delay3 gate_instance_list ';'
{ pform_makegates($2, str_strength, $3, $4, $1);
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/* Pullup and pulldown devices cannot have delays, and their
strengths are limited. */
| K_pullup gate_instance_list ';'
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
{ pform_makegates(PGBuiltin::PULLUP, pull_strength, 0,
$2, 0);
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
}
| K_pulldown gate_instance_list ';'
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
{ pform_makegates(PGBuiltin::PULLDOWN, pull_strength,
0, $2, 0);
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Accept single strengths for pullup and pulldown.
2001-04-29 00:56:15 +02:00
| K_pullup '(' dr_strength1 ')' gate_instance_list ';'
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
{ pform_makegates(PGBuiltin::PULLUP, $3, 0, $5, 0);
Accept single strengths for pullup and pulldown.
2001-04-29 00:56:15 +02:00
}
Add support for giving both strengths to a pull device. In the standard a pull device can be given both a 1 and 0 strength. Only the appropriate one is actually used. This patch adds support for giving both pull strength to a pull device.
2011-01-29 02:25:58 +01:00
| K_pullup '(' dr_strength1 ',' dr_strength0 ')' gate_instance_list ';'
{ pform_makegates(PGBuiltin::PULLUP, $3, 0, $7, 0);
}
| K_pullup '(' dr_strength0 ',' dr_strength1 ')' gate_instance_list ';'
{ pform_makegates(PGBuiltin::PULLUP, $5, 0, $7, 0);
}
Accept single strengths for pullup and pulldown.
2001-04-29 00:56:15 +02:00
| K_pulldown '(' dr_strength0 ')' gate_instance_list ';'
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
{ pform_makegates(PGBuiltin::PULLDOWN, $3, 0, $5, 0);
Accept single strengths for pullup and pulldown.
2001-04-29 00:56:15 +02:00
}
Add support for giving both strengths to a pull device. In the standard a pull device can be given both a 1 and 0 strength. Only the appropriate one is actually used. This patch adds support for giving both pull strength to a pull device.
2011-01-29 02:25:58 +01:00
| K_pulldown '(' dr_strength1 ',' dr_strength0 ')' gate_instance_list ';'
{ pform_makegates(PGBuiltin::PULLDOWN, $5, 0, $7, 0);
}
| K_pulldown '(' dr_strength0 ',' dr_strength1 ')' gate_instance_list ';'
{ pform_makegates(PGBuiltin::PULLDOWN, $3, 0, $7, 0);
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/* This rule handles instantiations of modules and user defined
primitives. These devices to not have delay lists or strengths,
but then can have parameter lists. */
Accept attributes in front of module instantiations.
2006-03-25 03:42:58 +01:00
| attribute_list_opt
IDENTIFIER parameter_value_opt gate_instance_list ';'
{ perm_string tmp1 = lex_strings.make($2);
pform_make_modgates(tmp1, $3, $4);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Accept attributes in front of module instantiations.
2006-03-25 03:42:58 +01:00
if ($1) delete $1;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Accept attributes in front of module instantiations.
2006-03-25 03:42:58 +01:00
| attribute_list_opt
IDENTIFIER parameter_value_opt error ';'
{ yyerror(@2, "error: Invalid module instantiation");
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Accept attributes in front of module instantiations.
2006-03-25 03:42:58 +01:00
if ($1) delete $1;
Handle instance array of port-less modules.
2004-09-05 20:09:47 +02:00
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/* Continuous assignment can have an optional drive strength, then
an optional delay3 that applies to all the assignments in the
Rename assign_list to cont_assign_list.
2007-04-21 06:45:36 +02:00
cont_assign_list. */
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Rename assign_list to cont_assign_list.
2007-04-21 06:45:36 +02:00
| K_assign drive_strength_opt delay3_opt cont_assign_list ';'
Carry assignment strength to pform.
2000-05-06 17:41:56 +02:00
{ pform_make_pgassign_list($4, $3, $2, @1.text, @1.first_line); }
Carry Verilog 2001 attributes with processes, all the way through to the ivl_target API. Divide signal reference counts between rval and lval references.
2002-05-26 03:39:02 +02:00
/* Always and initial items are behavioral processes. */
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
| attribute_list_opt K_always statement
Infrastructure for elaborating analog statements. Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
2008-10-22 07:15:49 +02:00
{ PProcess*tmp = pform_make_behavior(IVL_PR_ALWAYS, $3, $1);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
FILE_NAME(tmp, @2);
}
| attribute_list_opt K_initial statement
Infrastructure for elaborating analog statements. Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
2008-10-22 07:15:49 +02:00
{ PProcess*tmp = pform_make_behavior(IVL_PR_INITIAL, $3, $1);
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
FILE_NAME(tmp, @2);
}
Implement SystemVerilog final statements. Add a new IVL_PR_FINAL process type. Add a flag to NetScope in_final_ which is set when elaborating the statement of a final procedure. Add checks during statement elaboration for invalid statements in a final procedure, similar to checks for statements in functions. Do a final check to make sure no final blocks have delays. In the vvp runtime, use "$final" as the flag for the thread created by the final procedure. During compilation, instead of adding such a thread to the sched_list, add it to a new schedule_final_list that mirrors the schedule_init_list, but is run at the end of simulation.
2011-03-30 08:42:26 +02:00
| attribute_list_opt K_final statement
{ PProcess*tmp = pform_make_behavior(IVL_PR_FINAL, $3, $1);
FILE_NAME(tmp, @2);
}
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
| attribute_list_opt K_analog analog_statement
Infrastructure for elaborating analog statements. Put together the infrastructure for elaborating analog statements, including create the NetAnalogTop objects that hold analog statements and are in turn held by the design. While doing this, clean up the various unique initial/always enumerations to use the ivl_process_type_t type.
2008-10-22 07:15:49 +02:00
{ pform_make_analog_behavior(@2, IVL_PR_ALWAYS, $3); }
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| class_declaration
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
| task_declaration
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/* The function declaration rule matches the function declaration
header, then pushes the function scope. This causes the
definitions in the func_body to take on the scope of the function
instead of the module. */
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| K_function K_automatic_opt function_range_or_type_opt IDENTIFIER ';'
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ assert(current_function == 0);
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
current_function = pform_push_function_scope(@1, $4, $2);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
}
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
function_item_list statement_list
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
K_endfunction
Print an error for automatic tasks or functions. This patch adds code to recognize and report that automatic task or functions are not currently supported.
2008-08-13 22:58:49 +02:00
{ current_function->set_ports($7);
current_function->set_return($3);
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
assert($8 && $8->size() > 0);
if ($8->size() == 1) {
current_function->set_statement((*$8)[0]);
delete $8;
} else {
PBlock*tmp = new PBlock(PBlock::BL_SEQ);
FILE_NAME(tmp, @8);
tmp->set_statement( *$8 );
current_function->set_statement(tmp);
delete $8;
if (!gn_system_verilog()) {
yyerror(@8, "error: Function body with multiple statements requres SystemVerilog.");
}
}
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
pform_pop_scope();
current_function = 0;
Print an error for automatic tasks or functions. This patch adds code to recognize and report that automatic task or functions are not currently supported.
2008-08-13 22:58:49 +02:00
delete[]$4;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| K_function K_automatic_opt function_range_or_type_opt IDENTIFIER
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
{ assert(current_function == 0);
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
current_function = pform_push_function_scope(@1, $4, $2);
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
}
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
'(' tf_port_list_opt ')' ';'
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
block_item_decls_opt
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
statement_list
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
K_endfunction
Print an error for automatic tasks or functions. This patch adds code to recognize and report that automatic task or functions are not currently supported.
2008-08-13 22:58:49 +02:00
{ current_function->set_ports($7);
current_function->set_return($3);
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
assert($11 && $11->size() > 0);
if ($11->size() == 1) {
current_function->set_statement((*$11)[0]);
delete $11;
} else {
PBlock*tmp = new PBlock(PBlock::BL_SEQ);
FILE_NAME(tmp, @11);
tmp->set_statement( *$11 );
current_function->set_statement(tmp);
delete $11;
if (!gn_system_verilog()) {
yyerror(@11, "error: Function body with multiple statements requres SystemVerilog.");
}
}
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
pform_pop_scope();
current_function = 0;
Print an error for automatic tasks or functions. This patch adds code to recognize and report that automatic task or functions are not currently supported.
2008-08-13 22:58:49 +02:00
delete[]$4;
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
if ($7==0 && !gn_system_verilog()) {
Use the identifier to get the correct line information Using the closing ')' was not giving the correct line number.
2012-01-10 04:11:36 +01:00
yyerror(@4, "error: Empty parenthesis syntax requires SystemVerilog.");
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
}
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
}
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| K_function K_automatic_opt function_range_or_type_opt IDENTIFIER error K_endfunction
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
{ /* */
if (current_function) {
pform_pop_scope();
current_function = 0;
}
On error there is no need to pop the scope. The error routines for task and function definitions were incorrectly popping the scope. This should not be done since no scope was pushed. Also assert that the current_task/function is 0 to catch that kind of error like the other definition rules.
2010-06-13 20:41:24 +02:00
assert(current_function == 0);
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
yyerror(@1, "error: Syntax error defining function.");
yyerrok;
Print an error for automatic tasks or functions. This patch adds code to recognize and report that automatic task or functions are not currently supported.
2008-08-13 22:58:49 +02:00
delete[]$4;
Add better error recovery for failed task/function definition. This patch does a better job of recovering from an error in a task or function definition. This prevents the compiler from printing many irrelevant error messages.
2008-04-25 23:26:17 +02:00
}
User defined functions can have ANSI-style ports Update the rules for parsing user function definitions to allow Verilog-2001 ANSI style port declarations. In the process, also unify with the user task port declaration so that the types don't diverge. The rules are the same for both, with the extra constraint that function ports must all be input. This latter rule is checked later, during elaboration, so that the task/function pform code can be shared, and better error messages can be generated.
2008-04-19 06:33:03 +02:00
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/* A generate region can contain further module items. Actually, it
is supposed to be limited to certain kinds of module items, but
Detect generate regions within generate schemes. Generate schemes may nest freely, but generate regions (an anachronistic concept from 1364-2001) cannot nest, not within schemes or other regions. Have the parser detect the nesting and print an error message.
2010-03-12 01:06:02 +01:00
the semantic tests will check that for us. Do check that the
generate/endgenerate regions do not nest. Generate schemes nest,
but generate regions do not. */
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
| K_generate module_item_list_opt K_endgenerate
Detect generate regions within generate schemes. Generate schemes may nest freely, but generate regions (an anachronistic concept from 1364-2001) cannot nest, not within schemes or other regions. Have the parser detect the nesting and print an error message.
2010-03-12 01:06:02 +01:00
{ // Test for bad nesting. I understand it, but it is illegal.
if (pform_parent_generate()) {
cerr << @1 << ": error: Generate/endgenerate regions cannot nest." << endl;
cerr << @1 << ": : Try removing optional generate/endgenerate keywords," << endl;
cerr << @1 << ": : or move them to surround the parent generate scheme." << endl;
error_count += 1;
}
}
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
| K_genvar list_of_identifiers ';'
Add file and line information for parameters, etc. This patch adds file and line information for parameters and local parameters. It also adds file/line stubs for signals in the tgt-* files. It adds the pform code needed to eventually do genvar checks and passing of genvar file/line information. It verifies that a genvar does not have the same name as a parameter/local parameter.
2008-05-06 04:46:30 +02:00
{ pform_genvars(@1, $2); }
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
| K_for '(' IDENTIFIER '=' expression ';'
expression ';'
IDENTIFIER '=' expression ')'
{ pform_start_generate_for(@1, $3, $5, $7, $9, $11); }
generate_block
{ pform_endgenerate(); }
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
| generate_if
generate_block_opt
K_else
{ pform_start_generate_else(@1); }
generate_block
{ pform_endgenerate(); }
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
| generate_if
generate_block_opt %prec less_than_K_else
{ pform_endgenerate(); }
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
| K_case '(' expression ')'
{ pform_start_generate_case(@1, $3); }
generate_case_items
K_endcase
{ pform_endgenerate(); }
Detect and warn about anachronistic use of begin/end in generate. Verilog-2001 only allows a single generate item within a generate- endgenerate region, but allowed one to collect generate schemes with begin/end blocks. Verilog-2005 cleaned up that mess, and it is the 2005 syntax that Icarus Verilog implements. This patch detects the anachronistic use of begin/end within the generate region, ignores the begin/end words, and prints a warning that the user is using an obsolete syntax.
2008-06-19 05:33:30 +02:00
/* Handle some anachronistic syntax cases. */
| K_generate K_begin module_item_list_opt K_end K_endgenerate
{ /* Detect and warn about anachronistic begin/end use */
if (generation_flag > GN_VER2001) {
warn_count += 1;
cerr << @2 << ": warning: Anachronistic use of begin/end to surround generate schemes." << endl;
}
}
Add support for the 1364-2001 generate of a named block. This is obsolete in 1364-2005, but is supported 1364-2001. Icarus already supported generate with unnamed block.
2008-11-15 03:35:39 +01:00
| K_generate K_begin ':' IDENTIFIER {
Check for name space collisions. This patch adds code to check for most of the name space collisions. genvars are not checked correctly since they are not completely implemented.
2009-04-25 04:07:48 +02:00
pform_start_generate_nblock(@2, $4);
Add support for the 1364-2001 generate of a named block. This is obsolete in 1364-2005, but is supported 1364-2001. Icarus already supported generate with unnamed block.
2008-11-15 03:35:39 +01:00
} module_item_list_opt K_end K_endgenerate
{ /* Detect and warn about anachronistic named begin/end use */
if (generation_flag > GN_VER2001) {
warn_count += 1;
cerr << @2 << ": warning: Anachronistic use of named begin/end to surround generate schemes." << endl;
}
pform_endgenerate();
}
Detect and warn about anachronistic use of begin/end in generate. Verilog-2001 only allows a single generate item within a generate- endgenerate region, but allowed one to collect generate schemes with begin/end blocks. Verilog-2005 cleaned up that mess, and it is the 2005 syntax that Icarus Verilog implements. This patch detects the anachronistic use of begin/end within the generate region, ignores the begin/end words, and prints a warning that the user is using an obsolete syntax.
2008-06-19 05:33:30 +02:00
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
/* specify blocks are parsed but ignored. */
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| K_specify K_endspecify
{ /* empty lists are legal syntax. */ }
More parseable syntax.
1999-06-12 05:42:57 +02:00
| K_specify specify_item_list K_endspecify
{
}
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| K_specify error K_endspecify
{ yyerror(@1, "error: syntax error in specify block");
yyerrok;
}
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
/* These rules match various errors that the user can type into
module items. These rules try to catch them at a point where a
reasonable error message can be produced. */
Support arrays of integers.
2001-01-06 03:29:35 +01:00
[PATCH] Better error message when an endmodule is missing (nested modules). This patch adds better checking for a missing endmodule or an attempt to nest modules. A more descriptive message is printed and the location of the original module definition is printed.
2007-08-17 19:10:28 +02:00
| K_module error ';'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@1, "error: missing endmodule or attempt to "
[PATCH] Better error message when an endmodule is missing (nested modules). This patch adds better checking for a missing endmodule or an attempt to nest modules. A more descriptive message is printed and the location of the original module definition is printed.
2007-08-17 19:10:28 +02:00
"nest modules.");
pform_error_nested_modules();
yyerrok;
}
Better handling of module item errors.
2001-04-29 22:18:34 +02:00
| error ';'
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
{ yyerror(@2, "error: invalid module item.");
Better handling of module item errors.
2001-04-29 22:18:34 +02:00
yyerrok;
Support arrays of integers.
2001-01-06 03:29:35 +01:00
}
declaration initialization for time variables.
2001-01-06 07:31:58 +01:00
| K_assign error '=' expression ';'
{ yyerror(@1, "error: syntax error in left side "
"of continuous assignment.");
yyerrok;
}
| K_assign error ';'
{ yyerror(@1, "error: syntax error in "
"continuous assignment");
yyerrok;
}
Parse parameters within nested scopes.
2001-01-13 23:20:08 +01:00
| K_function error K_endfunction
{ yyerror(@1, "error: I give up on this "
"function definition.");
yyerrok;
}
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
/* These rules are for the Icarus Verilog specific $attribute
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
extensions. Then catch the parameters of the $attribute keyword. */
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
| KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')' ';'
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
{ perm_string tmp3 = lex_strings.make($3);
Addtrbute keys are perm_strings.
2004-02-20 19:53:33 +01:00
perm_string tmp5 = lex_strings.make($5);
pform_set_attrib(tmp3, tmp5, $7);
Make lexical token STRING new based. The STRING lexical token was malloc based, but then was passed to routines that are expecting a new based result. This patch standardizes on a new/delete based approach.
2009-01-09 02:03:33 +01:00
delete[] $3;
delete[] $5;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
}
| KK_attribute '(' error ')' ';'
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
{ yyerror(@1, "error: Malformed $attribute parameter list."); }
Fix up original SV timeunit/timeprecision patch. This patch modifies the original SystemVerilog timeunit/timeprecision patch in the following way: Removed trailing space. Reworked some code to use standard spacing rules. Added some comments. Combined some code. Major rework of local/global timeunit/timeprecision logic. Major rework of timeunit/timeprecision declaration/check code. This was needed to remove the shift/reduce warnings. Add a number of checks for invalid combinations.
2009-07-11 03:19:59 +02:00
| K_timeunit_check TIME_LITERAL ';'
{ pform_set_timeunit($2, true, true); }
| K_timeprecision_check TIME_LITERAL ';'
{ pform_set_timeprecision($2, true, true); }
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
generate_if : K_if '(' expression ')' { pform_start_generate_if(@1, $3); }
Deliver gate output strengths to the netlist.
2000-05-08 07:30:19 +02:00
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
generate_case_items
: generate_case_items generate_case_item
| generate_case_item
;
generate_case_item
Support direct nesting of conditional generate schemes. Verilog generate schemes support a special case where conditional generate schemes that contain only a nested conditional generate scheme do not create a new scope. Instead, it relies on the nested generate scheme to generate the scope.
2008-11-28 04:45:22 +01:00
: expression_list_proper ':' { pform_generate_case_item(@1, $1); } generate_block_opt
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
{ pform_endgenerate(); }
generate case items can have an optional statement. generate case supports optional statements by putting a ';' in place of the statement. This patch adds this functionality for all generate case items.
2008-10-24 03:03:38 +02:00
| K_default ':' { pform_generate_case_item(@1, 0); } generate_block_opt
Add support for generate case Generate case is a complex generate scheme where the items are sub-schemes of the case generate itself. The parser handles them something like nested generate statements, but storing the case guards as the test expression. Then the elaborator notes the case scheme and reaches into the case item schemes inside to make up tests, select the generate item, and elaborate.
2008-02-10 07:19:42 +01:00
{ pform_endgenerate(); }
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
module_item_list
: module_item_list module_item
| module_item
;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
module_item_list_opt
: module_item_list
|
;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
/* A generate block is the thing within a generate scheme. It may be
a single module item, an anonymous block of module items, or a
named module item. In all cases, the meat is in the module items
inside, and the processing is done by the module_item rules. We
only need to take note here of the scope name, if any. */
generate_block
: module_item
| K_begin module_item_list_opt K_end
| K_begin ':' IDENTIFIER module_item_list_opt K_end
{ pform_generate_block_name($3); }
;
Add support for conditional generate. In the process, fix bugs related to generate used multiple times by multiple scopes causing spurious generation results. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-22 04:04:48 +02:00
generate_block_opt : generate_block | ';' ;
Add support for generate loops w/ wires and gates.
2006-04-10 02:37:42 +02:00
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
Net declaration assignments.
1999-06-02 04:56:29 +02:00
/* A net declaration assignment allows the programmer to combine the
net declaration and the continuous assignment into a single
Remove C++ string from variable lists.
2000-10-31 18:00:04 +01:00
statement.
Note that the continuous assignment statement is generated as a
side effect, and all I pass up is the name of the l-value. */
Net declaration assignments.
1999-06-02 04:56:29 +02:00
net_decl_assign
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
: IDENTIFIER '=' expression
{ net_decl_assign_t*tmp = new net_decl_assign_t;
tmp->next = tmp;
tmp->name = lex_strings.make($1);
tmp->expr = $3;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = tmp;
}
;
Net declaration assignments.
1999-06-02 04:56:29 +02:00
net_decl_assigns
: net_decl_assigns ',' net_decl_assign
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
{ net_decl_assign_t*tmp = $1;
$3->next = tmp->next;
tmp->next = $3;
Net declaration assignments.
1999-06-02 04:56:29 +02:00
$$ = tmp;
}
| net_decl_assign
Properly parse net_decl assignments with delays.
2001-11-29 18:37:51 +01:00
{ $$ = $1;
Net declaration assignments.
1999-06-02 04:56:29 +02:00
}
;
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
primitive_type
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
: K_logic { $$ = IVL_VT_LOGIC; }
| K_bool { $$ = IVL_VT_BOOL; /* Icarus Verilog xtypes */}
| K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
| K_real { $$ = IVL_VT_REAL; }
;
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
Allow 'bit' and 'logic' function arguments SystemVerilog allows passing the 'bit' and 'logic' arguments to a function. The patch adds support for parsing these function definitions. The 'bit' data type is treated as boolean, whereas 'logic' data type remains as logic. Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-07 15:41:22 +02:00
bit_logic
: K_logic { $$ = IVL_VT_LOGIC; }
| K_bit { $$ = IVL_VT_BOOL; /* IEEE1800 / IEEE1364-2009 */}
;
Generalize signals to carry types.
2005-07-07 18:22:49 +02:00
primitive_type_opt : primitive_type { $$ = $1; } | { $$ = IVL_VT_NO_TYPE; } ;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
net_type
: K_wire { $$ = NetNet::WIRE; }
| K_tri { $$ = NetNet::TRI; }
| K_tri1 { $$ = NetNet::TRI1; }
| K_supply0 { $$ = NetNet::SUPPLY0; }
| K_wand { $$ = NetNet::WAND; }
| K_triand { $$ = NetNet::TRIAND; }
| K_tri0 { $$ = NetNet::TRI0; }
| K_supply1 { $$ = NetNet::SUPPLY1; }
| K_wor { $$ = NetNet::WOR; }
| K_trior { $$ = NetNet::TRIOR; }
Allow variables to implicitly convert to unresolved nets. SystemVerilog allows variables to be either variables or unresolved nets, depending on how they are used. If they are assigned by procedural code, then they are variables. If they are assigned by a continuous assignment, they are unresolved nets. Note that they cannot be both, and when they are unresolved nets they can only be assigned once.
2010-10-08 05:13:11 +02:00
| K_wone { $$ = NetNet::UNRESOLVED_WIRE;
Fix some keywords, add -g2001-noconfig and fix up uwire/wone. This patch adds -g2001-noconfig command line flag. The compiler already supported this with `begin_keywords. Document this in the manual page and fix a few other issues. Fix endgenerate to be a 2001 keyword and add a few missing keywords at the appropriate standard level e.g.(unsigned). Add uwire and deprecate wone. wone used to just convert without a warning to a wire. uwire will display a warning that it is being converted to a wire without a check. wone is converted to a uwire with a warning and then prints the uwire message. The uwire message will be replaced with a real check fairly soon.
2009-06-02 02:19:56 +02:00
cerr << @1.text << ":" << @1.first_line << ": warning: "
"'wone' is deprecated, please use 'uwire' "
"instead." << endl;
}
Allow variables to implicitly convert to unresolved nets. SystemVerilog allows variables to be either variables or unresolved nets, depending on how they are used. If they are assigned by procedural code, then they are variables. If they are assigned by a continuous assignment, they are unresolved nets. Note that they cannot be both, and when they are unresolved nets they can only be assigned once.
2010-10-08 05:13:11 +02:00
| K_uwire { $$ = NetNet::UNRESOLVED_WIRE; }
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
Parse port_declaration_lists from the 2001 Standard.
2002-05-20 01:37:28 +02:00
var_type
: K_reg { $$ = NetNet::REG; }
;
Support more parameter syntax.
2006-03-18 23:53:38 +01:00
/* In this rule we have matched the "parameter" keyword. The rule
generates a type (optional) and a list of assignments. */
Add support for module parameters.
1999-02-21 18:01:57 +01:00
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
parameter_assign_decl
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
: parameter_assign_list
| range
{ param_active_range = $1;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
Add support for parameter declarations with type but no range. The standard allows a parameter (or localparam) declaration of the form "parameter signed my_param = ...". The parser currently rejects this. A small adjustment is also required in the parameter evaluation code to correctly apply the type.
2011-12-03 13:11:28 +01:00
| K_signed
{ param_active_range = 0;
param_active_signed = true;
param_active_type = IVL_VT_LOGIC;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
| K_signed range
{ param_active_range = $2;
param_active_signed = true;
param_active_type = IVL_VT_LOGIC;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
| K_integer
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ param_active_range = make_range_from_width(integer_width);
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
param_active_signed = true;
param_active_type = IVL_VT_LOGIC;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
Add parameter time/realtime types and other fixes. This patch adds the time and realtime types to parameters and local parameters. It also makes the width (range) of an integer parameter match the variable "integer_width" (normally 32 bits). It also converts a real value to an integer when a range is implicitly or explicitly given. This all matches what the standard specifies. Fixed an error in converting -1 to a unsized verinum.
2008-06-12 01:47:43 +02:00
| K_time
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ param_active_range = make_range_from_width(64);
Add parameter time/realtime types and other fixes. This patch adds the time and realtime types to parameters and local parameters. It also makes the width (range) of an integer parameter match the variable "integer_width" (normally 32 bits). It also converts a real value to an integer when a range is implicitly or explicitly given. This all matches what the standard specifies. Fixed an error in converting -1 to a unsized verinum.
2008-06-12 01:47:43 +02:00
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
User task and function arguments can be time or realtime This patch adds the time and realtime properties for user task and function arguments. It also make a common rule for real and realtime since they are the same.
2008-08-09 03:12:52 +02:00
| real_or_realtime
Add parameter time/realtime types and other fixes. This patch adds the time and realtime types to parameters and local parameters. It also makes the width (range) of an integer parameter match the variable "integer_width" (normally 32 bits). It also converts a real value to an integer when a range is implicitly or explicitly given. This all matches what the standard specifies. Fixed an error in converting -1 to a unsized verinum.
2008-06-12 01:47:43 +02:00
{ param_active_range = 0;
param_active_signed = true;
param_active_type = IVL_VT_REAL;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
support parameters declared with atom2 types.
2012-01-16 20:04:02 +01:00
| atom2_type
{ param_active_range = make_range_from_width($1);
param_active_signed = true;
param_active_type = IVL_VT_BOOL;
}
parameter_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
;
Support parameters with defined ranges.
2002-08-19 04:39:16 +02:00
Add support for module parameters.
1999-02-21 18:01:57 +01:00
parameter_assign_list
: parameter_assign
| parameter_assign_list ',' parameter_assign
;
Support more parameter syntax.
2006-03-18 23:53:38 +01:00
parameter_assign
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
: IDENTIFIER '=' expression parameter_value_ranges_opt
{ PExpr*tmp = $3;
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
pform_set_parameter(@1, lex_strings.make($1), param_active_type,
param_active_signed, param_active_range, tmp, $4);
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
delete[]$1;
}
;
parameter_value_ranges_opt : parameter_value_ranges { $$ = $1; } | { $$ = 0; } ;
parameter_value_ranges
: parameter_value_ranges parameter_value_range
{ $$ = $2; $$->next = $1; }
| parameter_value_range
{ $$ = $1; $$->next = 0; }
;
parameter_value_range
: from_exclude '[' value_range_expression ':' value_range_expression ']'
{ $$ = pform_parameter_value_range($1, false, $3, false, $5); }
| from_exclude '[' value_range_expression ':' value_range_expression ')'
{ $$ = pform_parameter_value_range($1, false, $3, true, $5); }
| from_exclude '(' value_range_expression ':' value_range_expression ']'
{ $$ = pform_parameter_value_range($1, true, $3, false, $5); }
| from_exclude '(' value_range_expression ':' value_range_expression ')'
{ $$ = pform_parameter_value_range($1, true, $3, true, $5); }
Add support for exclude of a point Parameter value ranges support the exclude of a point as well as range, so add the syntax to support that case. Internally it is handled as a degenerate range, but the parse and initial elaboration need to know about it.
2008-06-06 06:49:49 +02:00
| K_exclude expression
{ $$ = pform_parameter_value_range(true, false, $2, false, $2); }
Parse parameter value ranges into pform. Handle parameter value ranges as far as the pform. The +-inf expressions are not handled yet, nor is the single value exclude, but the other cases are handled.
2008-05-13 06:26:38 +02:00
;
value_range_expression
: expression { $$ = $1; }
| K_inf { $$ = 0; }
| '+' K_inf { $$ = 0; }
| '-' K_inf { $$ = 0; }
;
from_exclude : K_from { $$ = false; } | K_exclude { $$ = true; } ;
Fix module parameter override syntax.
2000-01-02 00:47:58 +01:00
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
/* Localparam assignments and assignment lists are broken into
separate BNF so that I can call slightly different parameter
Support localparam.
2000-03-12 18:09:40 +01:00
handling code. They parse the same as parameters, they just
behave differently when someone tries to override them. */
localparam_assign
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
: IDENTIFIER '=' expression
{ PExpr*tmp = $3;
pform_set_localparam(@1, lex_strings.make($1),
param_active_type,
param_active_signed,
param_active_range, tmp);
delete[]$1;
}
;
Support localparam.
2000-03-12 18:09:40 +01:00
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
localparam_assign_decl
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
: localparam_assign_list
| range
{ param_active_range = $1;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
IVL_VT_LOGIC is default localparam type not IVL_VT_NO_TYPE This patch fixes a bug where a local parameter with only a range was incorrectly setting the default parameter type to IVL_VT_NO_TYPE. This would create a compile time assert for any untyped parameter/localparam immediately following it.
2008-07-16 22:58:16 +02:00
param_active_type = IVL_VT_LOGIC;
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
}
Add support for parameter declarations with type but no range. The standard allows a parameter (or localparam) declaration of the form "parameter signed my_param = ...". The parser currently rejects this. A small adjustment is also required in the parameter evaluation code to correctly apply the type.
2011-12-03 13:11:28 +01:00
| K_signed
{ param_active_range = 0;
param_active_signed = true;
param_active_type = IVL_VT_LOGIC;
}
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
| K_signed range
{ param_active_range = $2;
param_active_signed = true;
param_active_type = IVL_VT_LOGIC;
}
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
Fix default parameter type if localparams are present. localparam declarations were messing up the state of parser variables so that the default types of following parameters got messed up.
2008-06-05 23:38:56 +02:00
param_active_type = IVL_VT_LOGIC;
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
}
| K_integer
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ param_active_range = make_range_from_width(integer_width);
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
param_active_signed = true;
param_active_type = IVL_VT_LOGIC;
}
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
Fix default parameter type if localparams are present. localparam declarations were messing up the state of parser variables so that the default types of following parameters got messed up.
2008-06-05 23:38:56 +02:00
param_active_type = IVL_VT_LOGIC;
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
}
Add parameter time/realtime types and other fixes. This patch adds the time and realtime types to parameters and local parameters. It also makes the width (range) of an integer parameter match the variable "integer_width" (normally 32 bits). It also converts a real value to an integer when a range is implicitly or explicitly given. This all matches what the standard specifies. Fixed an error in converting -1 to a unsized verinum.
2008-06-12 01:47:43 +02:00
| K_time
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ param_active_range = make_range_from_width(64);
Add parameter time/realtime types and other fixes. This patch adds the time and realtime types to parameters and local parameters. It also makes the width (range) of an integer parameter match the variable "integer_width" (normally 32 bits). It also converts a real value to an integer when a range is implicitly or explicitly given. This all matches what the standard specifies. Fixed an error in converting -1 to a unsized verinum.
2008-06-12 01:47:43 +02:00
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
User task and function arguments can be time or realtime This patch adds the time and realtime properties for user task and function arguments. It also make a common rule for real and realtime since they are the same.
2008-08-09 03:12:52 +02:00
| real_or_realtime
Add parameter time/realtime types and other fixes. This patch adds the time and realtime types to parameters and local parameters. It also makes the width (range) of an integer parameter match the variable "integer_width" (normally 32 bits). It also converts a real value to an integer when a range is implicitly or explicitly given. This all matches what the standard specifies. Fixed an error in converting -1 to a unsized verinum.
2008-06-12 01:47:43 +02:00
{ param_active_range = 0;
param_active_signed = true;
param_active_type = IVL_VT_REAL;
}
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
Fix default parameter type if localparams are present. localparam declarations were messing up the state of parser variables so that the default types of following parameters got messed up.
2008-06-05 23:38:56 +02:00
param_active_type = IVL_VT_LOGIC;
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
}
support parameters declared with atom2 types.
2012-01-16 20:04:02 +01:00
| atom2_type
{ param_active_range = make_range_from_width($1);
param_active_signed = true;
param_active_type = IVL_VT_BOOL;
}
localparam_assign_list
{ param_active_range = 0;
param_active_signed = false;
param_active_type = IVL_VT_LOGIC;
}
Add support for explicit parameter types, including real. Before this, the types of parameters were always logic, only the width and signed-ness could be controlled. A parameter may take on implicit real values if the expression were real. With this patch, the type for the parameter can be explicitly set to logic or real. This also means that the parameter real valued expressions need to be more crefully treated, possibly with casting integral expressions to real values, or real expressions to integral values.
2008-05-18 01:25:58 +02:00
;
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
Support localparam.
2000-03-12 18:09:40 +01:00
localparam_assign_list
: localparam_assign
| localparam_assign_list ',' localparam_assign
;
Add support for localparam ranges.
2004-08-26 06:02:03 +02:00
Fix module parameter override syntax.
2000-01-02 00:47:58 +01:00
/* The parameters of a module instance can be overridden by writing
spelling in a comment.
2002-11-09 03:22:07 +01:00
a list of expressions in a syntax much like a delay list. (The
Fix module parameter override syntax.
2000-01-02 00:47:58 +01:00
difference being the list can have any length.) The pform that
attaches the expression list to the module checks that the
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
expressions are constant.
Although the BNF in IEEE1364-1995 implies that parameter value
lists must be in parentheses, in practice most compilers will
accept simple expressions outside of parentheses if there is only
one value, so I'll accept simple numbers here.
The parameter value by name syntax is OVI enhancement BTF-B06 as
approved by WG1364 on 6/28/1998. */
Fix module parameter override syntax.
2000-01-02 00:47:58 +01:00
parameter_value_opt
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
: '#' '(' expression_list_with_nuls ')'
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
{ struct parmvalue_t*tmp = new struct parmvalue_t;
tmp->by_order = $3;
tmp->by_name = 0;
$$ = tmp;
}
| '#' '(' parameter_value_byname_list ')'
{ struct parmvalue_t*tmp = new struct parmvalue_t;
tmp->by_order = 0;
tmp->by_name = $3;
$$ = tmp;
}
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
| '#' DEC_NUMBER
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
{ assert($2);
PENumber*tmp = new PENumber($2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
struct parmvalue_t*lst = new struct parmvalue_t;
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
lst->by_order = new list<PExpr*>;
lst->by_order->push_back(tmp);
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
lst->by_name = 0;
$$ = lst;
Fix a small bug in the extra digits warning. There were a couple places where a normal decimal number was accidentally setting the base for an unsized number. This is only a warning problem.
2008-03-06 01:36:27 +01:00
based_size = 0;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
}
Handle general constant expressions in delays.
2000-01-02 02:59:52 +01:00
| '#' error
{ yyerror(@1, "error: syntax error in parameter value "
"assignment list.");
$$ = 0;
}
Fix module parameter override syntax.
2000-01-02 00:47:58 +01:00
|
{ $$ = 0; }
;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
parameter_value_byname
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
: '.' IDENTIFIER '(' expression ')'
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
{ named_pexpr_t*tmp = new named_pexpr_t;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp->name = lex_strings.make($2);
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
tmp->parm = $4;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
$$ = tmp;
}
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
| '.' IDENTIFIER '(' ')'
Add language support for Verilog-2001 attribute syntax. Hook this support into existing $attribute handling, and add number and void value types. Add to the ivl_target API new functions for access of complex attributes attached to gates.
2002-05-23 05:08:50 +02:00
{ named_pexpr_t*tmp = new named_pexpr_t;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp->name = lex_strings.make($2);
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
tmp->parm = 0;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
$$ = tmp;
}
;
parameter_value_byname_list
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
: parameter_value_byname
{ list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
tmp->push_back(*$1);
delete $1;
$$ = tmp;
}
| parameter_value_byname_list ',' parameter_value_byname
{ list<named_pexpr_t>*tmp = $1;
tmp->push_back(*$3);
delete $3;
$$ = tmp;
}
;
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
Support named parameter override lists.
2000-01-09 06:50:48 +01:00
/* The port (of a module) is a fairly complex item. Each port is
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
handled as a Module::port_t object. A simple port reference has a
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
name and a PExpr object, but more complex constructs are possible
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
where the name can be attached to a list of PWire objects.
The port_reference returns a Module::port_t, and so does the
port_reference_list. The port_reference_list may have built up a
list of PWires in the port_t object, but it is still a single
Module::port_t object.
The port rule below takes the built up Module::port_t object and
tweaks its name as needed. */
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
port
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
: port_reference
{ $$ = $1; }
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
/* This syntax attaches an external name to the port reference so
that the caller can bind by name to non-trivial port
references. The port_t object gets its PWire from the
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
port_reference, but its name from the IDENTIFIER. */
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
| '.' IDENTIFIER '(' port_reference ')'
{ Module::port_t*tmp = $4;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp->name = lex_strings.make($2);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
$$ = tmp;
}
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
/* A port can also be a concatenation of port references. In this
case the port does not have a name available to the outside, only
positional parameter passing is possible here. */
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
| '{' port_reference_list '}'
{ Module::port_t*tmp = $2;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp->name = perm_string();
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
$$ = tmp;
}
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
Spelling patch (Larry Doolittle)
2002-06-11 05:34:33 +02:00
/* This attaches a name to a port reference concatenation list so
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
that parameter passing be name is possible. */
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
| '.' IDENTIFIER '(' '{' port_reference_list '}' ')'
{ Module::port_t*tmp = $5;
parameter keys are per_strings.
2004-02-20 07:22:56 +01:00
tmp->name = lex_strings.make($2);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
$$ = tmp;
}
;
Handle unconnected module ports.
1999-09-17 04:06:25 +02:00
port_opt
: port { $$ = $1; }
| { $$ = 0; }
;
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
/* The port_name rule is used with a module is being *instantiated*,
and not when it is being declared. See the port rule if you are
looking for the ports of a module declaration. */
port_name
: '.' IDENTIFIER '(' expression ')'
{ named_pexpr_t*tmp = new named_pexpr_t;
tmp->name = lex_strings.make($2);
tmp->parm = $4;
delete[]$2;
$$ = tmp;
}
| '.' IDENTIFIER '(' error ')'
{ yyerror(@3, "error: invalid port connection expression.");
named_pexpr_t*tmp = new named_pexpr_t;
tmp->name = lex_strings.make($2);
tmp->parm = 0;
delete[]$2;
$$ = tmp;
}
| '.' IDENTIFIER '(' ')'
{ named_pexpr_t*tmp = new named_pexpr_t;
tmp->name = lex_strings.make($2);
tmp->parm = 0;
delete[]$2;
$$ = tmp;
}
| '.' IDENTIFIER
{ named_pexpr_t*tmp = new named_pexpr_t;
tmp->name = lex_strings.make($2);
tmp->parm = new PEIdent(lex_strings.make($2), true);
FILE_NAME(tmp->parm, @1);
delete[]$2;
$$ = tmp;
}
Wildcard named port connections. Implements Section 23.3.2.4 of IEEE 1800-2009.
2009-11-26 18:39:21 +01:00
| K_DOTSTAR
{ named_pexpr_t*tmp = new named_pexpr_t;
tmp->name = lex_strings.make("*");
tmp->parm = 0;
$$ = tmp;
}
Enumeration element values can be expressions Allow more complex enumeration expressions, which means putting off the evaluation of the expression values until elaboration.
2010-11-13 03:47:06 +01:00
;
port_name_list
: port_name_list ',' port_name
{ list<named_pexpr_t>*tmp = $1;
tmp->push_back(*$3);
delete $3;
$$ = tmp;
}
| port_name
{ list<named_pexpr_t>*tmp = new list<named_pexpr_t>;
tmp->push_back(*$1);
delete $1;
$$ = tmp;
}
;
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
/* A port reference is an internal (to the module) name of the port,
possibly with a part of bit select to attach it to specific bits
of a signal fully declared inside the module.
The parser creates a PEIdent for every port reference, even if the
signal is bound to different ports. The elaboration figures out
the mess that this creates. The port_reference (and the
port_reference_list below) puts the port reference PEIdent into the
port_t object to pass it up to the module declaration code. */
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
port_reference
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
: IDENTIFIER
{ Module::port_t*ptmp;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
perm_string name = lex_strings.make($1);
ptmp = pform_module_port_reference(name, @1.text, @1.first_line);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
$$ = ptmp;
}
| IDENTIFIER '[' expression ':' expression ']'
Remove checks for constant expressions from the parser. This patch removes all the checks for constant expressions performed during the parsing phase, as these checks are (mostly) repeated during elaboration. It adds the missing check in the elaboration phase (the RHS of a register initialisation), and improves the error reporting and error recovery in other checks. This patch fixes pr2132552, which was caused by a fault in the parser constant expression checking.
2008-10-04 16:30:34 +02:00
{ index_component_t itmp;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
itmp.sel = index_component_t::SEL_PART;
itmp.msb = $3;
itmp.lsb = $5;
name_component_t ntmp (lex_strings.make($1));
ntmp.index.push_back(itmp);
pform_name_t pname;
pname.push_back(ntmp);
PEIdent*wtmp = new PEIdent(pname);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(wtmp, @1);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
Module::port_t*ptmp = new Module::port_t;
ptmp->name = perm_string();
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
ptmp->expr.push_back(wtmp);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
$$ = ptmp;
}
| IDENTIFIER '[' expression ']'
Remove checks for constant expressions from the parser. This patch removes all the checks for constant expressions performed during the parsing phase, as these checks are (mostly) repeated during elaboration. It adds the missing check in the elaboration phase (the RHS of a register initialisation), and improves the error reporting and error recovery in other checks. This patch fixes pr2132552, which was caused by a fault in the parser constant expression checking.
2008-10-04 16:30:34 +02:00
{ index_component_t itmp;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
itmp.sel = index_component_t::SEL_BIT;
itmp.msb = $3;
itmp.lsb = 0;
name_component_t ntmp (lex_strings.make($1));
ntmp.index.push_back(itmp);
pform_name_t pname;
pname.push_back(ntmp);
PEIdent*tmp = new PEIdent(pname);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
Module::port_t*ptmp = new Module::port_t;
ptmp->name = perm_string();
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
ptmp->expr.push_back(tmp);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
$$ = ptmp;
}
| IDENTIFIER '[' error ']'
{ yyerror(@1, "error: invalid port bit select");
Module::port_t*ptmp = new Module::port_t;
PEIdent*wtmp = new PEIdent(lex_strings.make($1));
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(wtmp, @1);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
ptmp->name = lex_strings.make($1);
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
ptmp->expr.push_back(wtmp);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
$$ = ptmp;
}
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Module ports are really special PEIdent expressions, because a name can be used many places in the port list.
2000-05-16 06:05:15 +02:00
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
port_reference_list
: port_reference
{ $$ = $1; }
| port_reference_list ',' port_reference
{ Module::port_t*tmp = $1;
Remove svector class from Module.h The goal is to completely remove the svector class because the standard vector class works perfectly well. This removes the uses in the Module.h header file.
2008-11-03 05:08:38 +01:00
append(tmp->expr, $3->expr);
Parse into pform arbitrarily complex module port declarations.
1999-08-03 06:14:49 +02:00
delete $3;
$$ = tmp;
}
;
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
port_direction /* IEEE1800-2005 A.1.3 */
: K_input { $$ = NetNet::PINPUT; }
| K_output { $$ = NetNet::POUTPUT; }
| K_inout { $$ = NetNet::PINOUT; }
;
port_direction_opt
: port_direction { $$ = $1; }
| { $$ = NetNet::PINPUT; }
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
/* The range is a list of variable dimensions. */
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
range
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
: variable_dimension
| range variable_dimension
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
{ list<PExpr*>*tmp = $1;
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
if ($2) tmp->splice(tmp->end(), *$2);
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
$$ = tmp;
}
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
range_opt
Parse multi-dimension packed arrays to pform.
2012-02-05 01:19:27 +01:00
: range
| { $$ = 0; }
;
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
dimensions_opt
: { $$ = 0; }
Remove shift/reduce problems from dimensions patch. This patch needs to be applied after the dimensions checking patch to remove the shift/reduce errors it created.
2007-11-14 05:49:05 +01:00
| dimensions { $$ = $1; }
dimensions
: '[' expression ':' expression ']'
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
{ list<index_component_t> *tmp = new list<index_component_t>;
index_component_t index;
index.msb = $2;
index.lsb = $4;
tmp->push_back(index);
$$ = tmp;
}
Allow SystemVerilog [size] dimension for unpacked arrays. IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by an address range, such as [1:1024], or a single positive number to specify the size of a fixed-size unpacked array, as in C. In other words, [size] becomes the same as [0:size-1]." This patch implements that translation in the parser. It issues a warning when doing so when the generation flag is less than 2005-sv.
2010-11-21 03:25:47 +01:00
| '[' expression ']'
{ if (generation_flag < GN_VER2005_SV) {
warn_count += 1;
cerr << @2 << ": warning: Use of SystemVerilog [size] dimension. "
<< "Use at least -g2005-sv to remove this warning." << endl;
}
list<index_component_t> *tmp = new list<index_component_t>;
index_component_t index;
index.msb = new PENumber(new verinum((uint64_t)0, integer_width));
index.lsb = new PEBinary('-', $2, new PENumber(new verinum((uint64_t)1, integer_width)));
tmp->push_back(index);
$$ = tmp;
}
Remove shift/reduce problems from dimensions patch. This patch needs to be applied after the dimensions checking patch to remove the shift/reduce errors it created.
2007-11-14 05:49:05 +01:00
| dimensions '[' expression ':' expression ']'
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
{ list<index_component_t> *tmp = $1;
index_component_t index;
index.msb = $3;
index.lsb = $5;
tmp->push_back(index);
$$ = tmp;
}
Allow SystemVerilog [size] dimension for unpacked arrays. IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by an address range, such as [1:1024], or a single positive number to specify the size of a fixed-size unpacked array, as in C. In other words, [size] becomes the same as [0:size-1]." This patch implements that translation in the parser. It issues a warning when doing so when the generation flag is less than 2005-sv.
2010-11-21 03:25:47 +01:00
| dimensions '[' expression ']'
{ if (generation_flag < GN_VER2005_SV) {
warn_count += 1;
cerr << @2 << ": warning: Use of SystemVerilog [size] dimension. "
<< "Use at least -g2005-sv to remove this warning." << endl;
}
list<index_component_t> *tmp = $1;
index_component_t index;
index.msb = new PENumber(new verinum((uint64_t)0, integer_width));
index.lsb = new PEBinary('-', $3, new PENumber(new verinum((uint64_t)1, integer_width)));
tmp->push_back(index);
$$ = tmp;
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
Support integer for function return value.
2001-12-07 06:03:13 +01:00
/* This is used to express the return type of a function. */
Rewire/generalize parsing an elaboration of function return values to allow for better speed and more type support.
2004-06-01 01:34:36 +02:00
function_range_or_type_opt
Function definition without return type The patch allows parsing of function definitions which do not have explicit data type or range. The default return data type is assumed to be reg unsigned and the default range is 0. Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-06-30 14:03:29 +02:00
: unsigned_signed_opt range_opt
{
/* the default type is reg unsigned and no range */
$$.type = PTF_REG;
$$.range = 0;
if ($1)
$$.type = PTF_REG_S;
if ($2)
$$.range = make_range_vector($2);
}
Explicit 'reg' return type in function definition Verilog allows returning variables of 'reg' type. The icarus verilog implicitly assumes the default returned type of the function as 'reg unsigned'. The patch allows to explicitly specify the 'reg' return type. Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-06-29 14:40:04 +02:00
| K_reg unsigned_signed_opt range_opt
{
/* the default type is reg unsigned and no range */
$$.type = PTF_REG;
$$.range = 0;
if ($2)
$$.type = PTF_REG_S;
if ($3)
$$.range = make_range_vector($3);
}
Support bit/logic return from functions. Acked-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-11 15:06:11 +02:00
| bit_logic unsigned_signed_opt range_opt
{
/* the default type is bit/logic unsigned and no range */
$$.type = PTF_REG;
$$.range = 0;
if ($2)
$$.type = PTF_REG_S;
if ($3)
$$.range = make_range_vector($3);
}
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
| K_integer { $$.range = 0; $$.type = PTF_INTEGER; }
| K_real { $$.range = 0; $$.type = PTF_REAL; }
| K_realtime { $$.range = 0; $$.type = PTF_REALTIME; }
| K_time { $$.range = 0; $$.type = PTF_TIME; }
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
| atom2_type { $$.range = make_range_vector($1); $$.type = PTF_ATOM2_S; }
| atom2_type K_signed { $$.range = make_range_vector($1); $$.type = PTF_ATOM2_S; }
| atom2_type K_unsigned { $$.range = make_range_vector($1); $$.type = PTF_ATOM2; }
Tasks functions with atom2 arguments. Parse 2-value atoms as arguments to functions and tasks.
2010-10-03 01:29:30 +02:00
;
parse real and realtime declarations.
2000-12-05 23:32:05 +01:00
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
/* The register_variable rule is matched only when I am parsing
variables in a "reg" definition. I therefore know that I am
creating registers and I do not need to let the containing rule
handle it. The register variable list simply packs them together
so that bit ranges can be assigned. */
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
register_variable
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
: IDENTIFIER dimensions_opt
{ perm_string ident_name = lex_strings.make($1);
pform_makewire(@1, ident_name, NetNet::REG,
NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
if ($2 != 0) {
index_component_t index;
if ($2->size() > 1) {
yyerror(@2, "sorry: only 1 dimensional arrays "
"are currently supported.");
}
index = $2->front();
pform_set_reg_idx(ident_name, index.msb, index.lsb);
delete $2;
}
$$ = $1;
}
| IDENTIFIER '=' expression
{ perm_string ident_name = lex_strings.make($1);
pform_makewire(@1, ident_name, NetNet::REG,
NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
pform_make_reginit(@1, ident_name, $3);
$$ = $1;
}
;
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
register_variable_list
: register_variable
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($1));
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
$$ = tmp;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
delete[]$1;
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
}
| register_variable_list ',' register_variable
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
$$ = tmp;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
delete[]$3;
Add memories to the parse and elaboration phases.
1999-04-19 03:59:36 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
;
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
/* TODO: Replace register_variable_list with list_of_variable_decl_assignments. */
list_of_variable_decl_assignments
: variable_decl_assignment
{ list<decl_assignment_t*>*tmp = new list<decl_assignment_t*>;
tmp->push_back($1);
$$ = tmp;
}
| list_of_variable_decl_assignments ',' variable_decl_assignment
{ list<decl_assignment_t*>*tmp = $1;
tmp->push_back($3);
$$ = tmp;
}
;
variable_decl_assignment
: IDENTIFIER dimensions_opt
{ decl_assignment_t*tmp = new decl_assignment_t;
tmp->name = lex_strings.make($1);
if ($2) {
tmp->index = *$2;
delete $2;
}
delete[]$1;
$$ = tmp;
}
| IDENTIFIER '=' expression
{ decl_assignment_t*tmp = new decl_assignment_t;
tmp->name = lex_strings.make($1);
tmp->expr .reset($3);
delete[]$1;
$$ = tmp;
}
;
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
real_variable
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
: IDENTIFIER dimensions_opt
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ perm_string name = lex_strings.make($1);
pform_makewire(@1, name, NetNet::REG, NetNet::NOT_A_PORT, IVL_VT_REAL, 0);
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
if ($2 != 0) {
Add support for real/realtime arrays. Support arrays of realtime variable arrays and net arrays. This involved a simple fix to the ivl core parser, proper support in the code generator, and rework the runtime support in vvp.
2008-11-02 04:44:03 +01:00
index_component_t index;
if ($2->size() > 1) {
yyerror(@2, "sorry: only 1 dimensional arrays "
"are currently supported.");
}
index = $2->front();
pform_set_reg_idx(name, index.msb, index.lsb);
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
delete $2;
Display an error for currently invalid number of array dimensions. Most types in Icarus support a single array dimension (reals do not support arrays at all). If you try to use an invalid number of dimensions the parser will now display an error message.
2007-11-07 23:18:36 +01:00
}
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
$$ = $1;
}
| IDENTIFIER '=' expression
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ perm_string name = lex_strings.make($1);
pform_makewire(@1, name, NetNet::REG, NetNet::NOT_A_PORT, IVL_VT_REAL, 0);
pform_make_reginit(@1, name, $3);
Initialize assignments of reals Support initialization assignments of real value variables. In the process, clean up the processing of real variable declarations in the parser. Signed-off-by: Stephen Williams <steve@icarus.com>
2007-08-05 06:50:06 +02:00
$$ = $1;
}
;
real_variable_list
: real_variable
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($1));
$$ = tmp;
delete[]$1;
}
| real_variable_list ',' real_variable
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
$$ = tmp;
delete[]$3;
}
;
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
net_variable
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
: IDENTIFIER dimensions_opt
{ perm_string name = lex_strings.make($1);
pform_makewire(@1, name, NetNet::IMPLICIT,
NetNet::NOT_A_PORT, IVL_VT_NO_TYPE, 0);
if ($2 != 0) {
index_component_t index;
if ($2->size() > 1) {
yyerror(@2, "sorry: only 1 dimensional arrays "
"are currently supported.");
}
index = $2->front();
pform_set_reg_idx(name, index.msb, index.lsb);
delete $2;
}
$$ = $1;
}
;
Major rework of array handling. Memories are replaced with the more general concept of arrays. The NetMemory and NetEMemory classes are removed from the ivl core program, and the IVL_LPM_RAM lpm type is removed from the ivl_target API.
2007-01-16 06:44:14 +01:00
net_variable_list
: net_variable
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($1));
$$ = tmp;
delete[]$1;
}
| net_variable_list ',' net_variable
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
$$ = tmp;
delete[]$3;
}
;
More parseable syntax.
1999-06-12 05:42:57 +02:00
specify_item
: K_specparam specparam_list ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| specify_simple_path_decl ';'
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
{ pform_module_specify_path($1);
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
}
| specify_edge_path_decl ';'
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
{ pform_module_specify_path($1);
Parse specify delay values.
2000-09-23 05:04:10 +02:00
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| K_if '(' expression ')' specify_simple_path_decl ';'
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
{ PSpecPath*tmp = $5;
Add support for conditional specify delay paths.
2007-03-01 07:19:38 +01:00
if (tmp) {
tmp->conditional = true;
tmp->condition = $3;
}
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
pform_module_specify_path(tmp);
Parse some more specify syntax.
1999-06-19 05:21:21 +02:00
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| K_if '(' expression ')' specify_edge_path_decl ';'
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
{ PSpecPath*tmp = $5;
if (tmp) {
tmp->conditional = true;
tmp->condition = $3;
}
pform_module_specify_path(tmp);
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
}
Parse specify ifnone statements.
2006-04-17 06:35:49 +02:00
| K_ifnone specify_simple_path_decl ';'
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
{ PSpecPath*tmp = $2;
if (tmp) {
tmp->conditional = true;
tmp->condition = 0;
}
pform_module_specify_path(tmp);
Parse specify ifnone statements.
2006-04-17 06:35:49 +02:00
}
Add a warning that ifnone with an edge-sensitive path is not supported. Cadence allows an ifnone with an edge-sensitive path. Until we understand exactly what this is and how to implement it this patch adds a warning that an ifnone with an edge-sensitive path is not supported.
2010-12-15 00:35:16 +01:00
| K_ifnone specify_edge_path_decl ';'
{ yyerror(@1, "Sorry: ifnone with an edge-sensitive path is "
"not supported.");
yyerrok;
}
Parse all the 1364-1995 and 1364-2001 timing checks. This patch adds code to parse and ignore the following timing checks: $nochange 1364-1995 $skew 1364-1995 $fullskew 1364-2001 $removal 1364-2001 $timeskew 1364-2001 The other checks were already supported. These have not been tested, but they use the same basic terms as the other checks. We can fully test these when we actually implement them.
2009-06-04 00:02:32 +02:00
| K_Sfullskew '(' spec_reference_event ',' spec_reference_event
',' delay_value ',' delay_value spec_notifier_opt ')' ';'
{ delete $7;
delete $9;
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| K_Shold '(' spec_reference_event ',' spec_reference_event
Fix parse errors related to pr766.
2005-07-27 16:54:51 +02:00
',' delay_value spec_notifier_opt ')' ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
{ delete $7;
}
Parse all the 1364-1995 and 1364-2001 timing checks. This patch adds code to parse and ignore the following timing checks: $nochange 1364-1995 $skew 1364-1995 $fullskew 1364-2001 $removal 1364-2001 $timeskew 1364-2001 The other checks were already supported. These have not been tested, but they use the same basic terms as the other checks. We can fully test these when we actually implement them.
2009-06-04 00:02:32 +02:00
| K_Snochange '(' spec_reference_event ',' spec_reference_event
',' delay_value ',' delay_value spec_notifier_opt ')' ';'
{ delete $7;
delete $9;
}
Fix syntax for $period to allow min:Ltyp:max expressions.
2004-09-05 23:01:51 +02:00
| K_Speriod '(' spec_reference_event ',' delay_value
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
spec_notifier_opt ')' ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
{ delete $5;
}
| K_Srecovery '(' spec_reference_event ',' spec_reference_event
Fix parse errors related to pr766.
2005-07-27 16:54:51 +02:00
',' delay_value spec_notifier_opt ')' ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
{ delete $7;
}
Parse all the 1364-1995 and 1364-2001 timing checks. This patch adds code to parse and ignore the following timing checks: $nochange 1364-1995 $skew 1364-1995 $fullskew 1364-2001 $removal 1364-2001 $timeskew 1364-2001 The other checks were already supported. These have not been tested, but they use the same basic terms as the other checks. We can fully test these when we actually implement them.
2009-06-04 00:02:32 +02:00
| K_Srecrem '(' spec_reference_event ',' spec_reference_event
',' delay_value ',' delay_value spec_notifier_opt ')' ';'
{ delete $7;
delete $9;
}
| K_Sremoval '(' spec_reference_event ',' spec_reference_event
',' delay_value spec_notifier_opt ')' ';'
{ delete $7;
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| K_Ssetup '(' spec_reference_event ',' spec_reference_event
Fix parse errors related to pr766.
2005-07-27 16:54:51 +02:00
',' delay_value spec_notifier_opt ')' ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
{ delete $7;
}
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
| K_Ssetuphold '(' spec_reference_event ',' spec_reference_event
min:typ:max delay values in specify statements.
2003-09-21 23:16:05 +02:00
',' delay_value ',' delay_value spec_notifier_opt ')' ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
{ delete $7;
delete $9;
}
Parse all the 1364-1995 and 1364-2001 timing checks. This patch adds code to parse and ignore the following timing checks: $nochange 1364-1995 $skew 1364-1995 $fullskew 1364-2001 $removal 1364-2001 $timeskew 1364-2001 The other checks were already supported. These have not been tested, but they use the same basic terms as the other checks. We can fully test these when we actually implement them.
2009-06-04 00:02:32 +02:00
| K_Sskew '(' spec_reference_event ',' spec_reference_event
',' delay_value spec_notifier_opt ')' ';'
{ delete $7;
}
| K_Stimeskew '(' spec_reference_event ',' spec_reference_event
',' delay_value spec_notifier_opt ')' ';'
Add $recrem to specify syntax.
2003-08-31 23:14:28 +02:00
{ delete $7;
}
min:typ:max delay values in specify statements.
2003-09-21 23:16:05 +02:00
| K_Swidth '(' spec_reference_event ',' delay_value ',' expression
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
spec_notifier_opt ')' ';'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
{ delete $5;
delete $7;
}
Fix parse errors related to pr766.
2005-07-27 16:54:51 +02:00
| K_Swidth '(' spec_reference_event ',' delay_value ')' ';'
threshold of $width is optional.
2001-10-14 04:03:51 +02:00
{ delete $5;
}
Ignore specify pulsestyle_* and *showcancelled directives. This patch adds code to silently ignore the specify directives: pulsestyle_onevent pulsestyle_ondetect showcancelled noshowcancelled.
2009-06-06 01:12:17 +02:00
| K_pulsestyle_onevent specify_path_identifiers ';'
{ delete $2;
}
| K_pulsestyle_ondetect specify_path_identifiers ';'
{ delete $2;
}
| K_showcancelled specify_path_identifiers ';'
{ delete $2;
}
| K_noshowcancelled specify_path_identifiers ';'
{ delete $2;
}
More parseable syntax.
1999-06-12 05:42:57 +02:00
;
specify_item_list
: specify_item
| specify_item_list specify_item
;
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
specify_edge_path_decl
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
: specify_edge_path '=' '(' delay_value_list ')'
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
{ $$ = pform_assign_path_delay($1, $4); }
specify delay can take an unbracketed simple value.
2002-11-26 04:56:10 +01:00
| specify_edge_path '=' delay_value_simple
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($3);
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
$$ = pform_assign_path_delay($1, tmp);
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
;
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
edge_operator : K_posedge { $$ = true; } | K_negedge { $$ = false; } ;
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
specify_edge_path
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
: '(' specify_path_identifiers spec_polarity
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
K_EG '(' specify_path_identifiers polarity_operator expression ')' ')'
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
{ int edge_flag = 0;
$$ = pform_make_specify_edge_path(@1, edge_flag, $2, $3, false, $6, $8); }
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
| '(' edge_operator specify_path_identifiers spec_polarity
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
K_EG '(' specify_path_identifiers polarity_operator expression ')' ')'
{ int edge_flag = $2? 1 : -1;
$$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, false, $7, $9);}
| '(' specify_path_identifiers spec_polarity
K_SG '(' specify_path_identifiers polarity_operator expression ')' ')'
{ int edge_flag = 0;
$$ = pform_make_specify_edge_path(@1, edge_flag, $2, $3, true, $6, $8); }
Parse all specify paths to pform.
2007-02-12 02:52:21 +01:00
| '(' edge_operator specify_path_identifiers spec_polarity
K_SG '(' specify_path_identifiers polarity_operator expression ')' ')'
Parse edge sensitive paths without edge specifier.
2007-04-13 04:34:35 +02:00
{ int edge_flag = $2? 1 : -1;
$$ = pform_make_specify_edge_path(@1, edge_flag, $3, $4, true, $7, $9); }
Handle more path polarity cases.
2001-08-31 23:08:35 +02:00
;
polarity_operator
: K_PO_POS
| K_PO_NEG
| ':'
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
;
specify_simple_path_decl
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
: specify_simple_path '=' '(' delay_value_list ')'
{ $$ = pform_assign_path_delay($1, $4); }
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| specify_simple_path '=' delay_value_simple
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*tmp = new list<PExpr*>;
tmp->push_back($3);
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
$$ = pform_assign_path_delay($1, tmp);
}
Handle index identifiers in simple paths.
2001-12-01 03:42:39 +01:00
| specify_simple_path '=' '(' error ')'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@3, "Syntax error in delay value list.");
Handle index identifiers in simple paths.
2001-12-01 03:42:39 +01:00
yyerrok;
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
$$ = 0;
Handle index identifiers in simple paths.
2001-12-01 03:42:39 +01:00
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
;
Parse some more specify syntax.
1999-06-19 05:21:21 +02:00
specify_simple_path
specparams as far as pform.
2003-02-27 07:45:11 +01:00
: '(' specify_path_identifiers spec_polarity
K_EG specify_path_identifiers ')'
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
{ $$ = pform_make_specify_path(@1, $2, $3, false, $5); }
specparams as far as pform.
2003-02-27 07:45:11 +01:00
| '(' specify_path_identifiers spec_polarity
K_SG specify_path_identifiers ')'
Basic support for specify timing.
2006-09-23 06:57:19 +02:00
{ $$ = pform_make_specify_path(@1, $2, $3, true, $5); }
Handle index identifiers in simple paths.
2001-12-01 03:42:39 +01:00
| '(' error ')'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@1, "Invalid simple path");
Handle index identifiers in simple paths.
2001-12-01 03:42:39 +01:00
yyerrok;
}
Generate code for disable.
2001-04-21 02:55:46 +02:00
;
specify_path_identifiers
specparams as far as pform.
2003-02-27 07:45:11 +01:00
: IDENTIFIER
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($1));
specparams as far as pform.
2003-02-27 07:45:11 +01:00
$$ = tmp;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
delete[]$1;
specparams as far as pform.
2003-02-27 07:45:11 +01:00
}
| IDENTIFIER '[' expr_primary ']'
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($1));
specparams as far as pform.
2003-02-27 07:45:11 +01:00
$$ = tmp;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
delete[]$1;
specparams as far as pform.
2003-02-27 07:45:11 +01:00
}
| specify_path_identifiers ',' IDENTIFIER
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
specparams as far as pform.
2003-02-27 07:45:11 +01:00
$$ = tmp;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
delete[]$3;
specparams as far as pform.
2003-02-27 07:45:11 +01:00
}
| specify_path_identifiers ',' IDENTIFIER '[' expr_primary ']'
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
specparams as far as pform.
2003-02-27 07:45:11 +01:00
$$ = tmp;
More identifier lists use perm_strings.
2004-05-25 21:21:06 +02:00
delete[]$3;
specparams as far as pform.
2003-02-27 07:45:11 +01:00
}
Parse some more specify syntax.
1999-06-19 05:21:21 +02:00
;
More parseable syntax.
1999-06-12 05:42:57 +02:00
specparam
: IDENTIFIER '=' expression
specparams as far as pform.
2003-02-27 07:45:11 +01:00
{ PExpr*tmp = $3;
Hande specparam with min/myp/max values.
2007-02-13 05:39:25 +01:00
pform_set_specparam(lex_strings.make($1), tmp);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
More parseable syntax.
1999-06-12 05:42:57 +02:00
}
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
| IDENTIFIER '=' expression ':' expression ':' expression
Hande specparam with min/myp/max values.
2007-02-13 05:39:25 +01:00
{ PExpr*tmp = 0;
switch (min_typ_max_flag) {
case MIN:
tmp = $3;
delete $5;
delete $7;
break;
case TYP:
delete $3;
tmp = $5;
delete $7;
break;
case MAX:
delete $3;
delete $5;
tmp = $7;
break;
}
Make min/typ/max default warning message universal. The min/typ/max default warning was not being produced in all locations a min/typ/max expression could be used. This patch adds the default warning code to all locations. It also modifies the manual page to explicitly state that only the first ten warnings are printed.
2007-11-21 20:07:40 +01:00
if (min_typ_max_warn > 0) {
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
cerr << tmp->get_fileline() << ": warning: choosing ";
Make min/typ/max default warning message universal. The min/typ/max default warning was not being produced in all locations a min/typ/max expression could be used. This patch adds the default warning code to all locations. It also modifies the manual page to explicitly state that only the first ten warnings are printed.
2007-11-21 20:07:40 +01:00
switch (min_typ_max_flag) {
case MIN:
cerr << "min";
break;
case TYP:
cerr << "typ";
break;
case MAX:
cerr << "max";
break;
}
cerr << " expression." << endl;
min_typ_max_warn -= 1;
}
Hande specparam with min/myp/max values.
2007-02-13 05:39:25 +01:00
pform_set_specparam(lex_strings.make($1), tmp);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
}
PATHPULSE specparam assignment syntax.
2002-11-21 18:40:11 +01:00
| PATHPULSE_IDENTIFIER '=' expression
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
{ delete[]$1;
PATHPULSE specparam assignment syntax.
2002-11-21 18:40:11 +01:00
delete $3;
Parse specparam parsepulse assignments.
2001-11-06 03:52:19 +01:00
}
| PATHPULSE_IDENTIFIER '=' '(' expression ',' expression ')'
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
{ delete[]$1;
Parse specparam parsepulse assignments.
2001-11-06 03:52:19 +01:00
delete $4;
delete $6;
}
More parseable syntax.
1999-06-12 05:42:57 +02:00
;
specparam_list
: specparam
| specparam_list ',' specparam
;
specparams as far as pform.
2003-02-27 07:45:11 +01:00
spec_polarity
: '+' { $$ = '+'; }
| '-' { $$ = '-'; }
| { $$ = 0; }
;
Parse some more specify syntax.
1999-06-19 05:21:21 +02:00
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
spec_reference_event
Detect and ignore specify edge expressions
2007-06-14 05:50:00 +02:00
: K_posedge expression
{ delete $2; }
| K_negedge expression
{ delete $2; }
| K_posedge expr_primary K_TAND expression
{ delete $2;
delete $4;
}
| K_negedge expr_primary K_TAND expression
{ delete $2;
delete $4;
}
Edge-control does not require conditional event This patch allows the edge control to be used without a conditional event.
2008-01-10 02:06:01 +01:00
| K_edge '[' edge_descriptor_list ']' expr_primary
{ delete $5; }
Detect and ignore specify edge expressions
2007-06-14 05:50:00 +02:00
| K_edge '[' edge_descriptor_list ']' expr_primary K_TAND expression
{ delete $5;
delete $7;
}
| expr_primary K_TAND expression
{ delete $1;
delete $3;
}
| expr_primary
{ delete $1; }
;
/* The edge_descriptor is detected by the lexor as the various
2-letter edge sequences that are supported here. For now, we
don't care what they are, because we do not yet support specify
edge events. */
edge_descriptor_list
: edge_descriptor_list ',' K_edge_descriptor
| K_edge_descriptor
;
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
spec_notifier_opt
: /* empty */
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
{ }
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
| spec_notifier
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
{ }
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
;
spec_notifier
: ','
Add a waring that timing check delayed signals will not be driven. The $setuphold and $recrem timing checks can create delayed signals that are needed to get a model to work correctly when negative timing check values are used. Since we do not support timing checks and just ignore them this can create simulation problems when a user tries to use these delayed signals since they are not driven. This patch adds a waring when the circuit is being compiled that these delayed signals will not be driven. This will be needed until we get time to add the real timing checks are mimic the delayed properties of the timing check.
2009-10-31 03:16:42 +01:00
{ args_after_notifier = 0; }
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| ',' hierarchy_identifier
Add a waring that timing check delayed signals will not be driven. The $setuphold and $recrem timing checks can create delayed signals that are needed to get a model to work correctly when negative timing check values are used. Since we do not support timing checks and just ignore them this can create simulation problems when a user tries to use these delayed signals since they are not driven. This patch adds a waring when the circuit is being compiled that these delayed signals will not be driven. This will be needed until we get time to add the real timing checks are mimic the delayed properties of the timing check.
2009-10-31 03:16:42 +01:00
{ args_after_notifier = 0; delete $2; }
Clean up spurious trailing white space.
2004-10-04 03:10:51 +02:00
| spec_notifier ','
Add a waring that timing check delayed signals will not be driven. The $setuphold and $recrem timing checks can create delayed signals that are needed to get a model to work correctly when negative timing check values are used. Since we do not support timing checks and just ignore them this can create simulation problems when a user tries to use these delayed signals since they are not driven. This patch adds a waring when the circuit is being compiled that these delayed signals will not be driven. This will be needed until we get time to add the real timing checks are mimic the delayed properties of the timing check.
2009-10-31 03:16:42 +01:00
{ args_after_notifier += 1; }
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| spec_notifier ',' hierarchy_identifier
Add a waring that timing check delayed signals will not be driven. The $setuphold and $recrem timing checks can create delayed signals that are needed to get a model to work correctly when negative timing check values are used. Since we do not support timing checks and just ignore them this can create simulation problems when a user tries to use these delayed signals since they are not driven. This patch adds a waring when the circuit is being compiled that these delayed signals will not be driven. This will be needed until we get time to add the real timing checks are mimic the delayed properties of the timing check.
2009-10-31 03:16:42 +01:00
{ args_after_notifier += 1;
if (args_after_notifier >= 3) {
cerr << @3 << ": warning: timing checks are not supported "
"and delayed signal \"" << *$3
<< "\" will not be driven." << endl;
}
delete $3; }
/* How do we match this path? */
spec reference events can be identifiers.
2001-10-09 20:11:58 +02:00
| IDENTIFIER
Add a waring that timing check delayed signals will not be driven. The $setuphold and $recrem timing checks can create delayed signals that are needed to get a model to work correctly when negative timing check values are used. Since we do not support timing checks and just ignore them this can create simulation problems when a user tries to use these delayed signals since they are not driven. This patch adds a waring when the circuit is being compiled that these delayed signals will not be driven. This will be needed until we get time to add the real timing checks are mimic the delayed properties of the timing check.
2009-10-31 03:16:42 +01:00
{ args_after_notifier = 0; delete[]$1; }
Parse a lot more specify syntax.
2001-07-02 01:44:43 +02:00
;
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
more specify syntax (Stehpan Boettcher)
2001-10-26 05:22:56 +02:00
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
statement /* This is roughly statement_item in the LRM */
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
/* assign and deassign statements are procedural code to do
structural assignments, and to turn that structural assignment
Spelling fixes Mostly then/than confusion. All comments or README files, except for one user-visible change in a tgt-vlog95 error message.
2011-03-11 20:27:54 +01:00
off. This is stronger than any other assign, but weaker than the
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
force assignments. */
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
: K_assign lpvalue '=' expression ';'
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
{ PCAssign*tmp = new PCAssign($2, $4);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
$$ = tmp;
}
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
| K_deassign lpvalue ';'
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
{ PDeassign*tmp = new PDeassign($2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
$$ = tmp;
}
/* Force and release statements are similar to assignments,
syntactically, but they will be elaborated differently. */
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
| K_force lpvalue '=' expression ';'
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
{ PForce*tmp = new PForce($2, $4);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
$$ = tmp;
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
}
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
| K_release lpvalue ';'
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
{ PRelease*tmp = new PRelease($2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
$$ = tmp;
}
/* begin-end blocks come in a variety of forms, including named and
anonymous. The named blocks can also carry their own reg
variables, which are placed in the scope created by the block
Spelling fixes Mostly then/than confusion. All comments or README files, except for one user-visible change in a tgt-vlog95 error message.
2011-03-11 20:27:54 +01:00
name. These are handled by pushing the scope name, then matching
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
the declarations. The scope is popped at the end of the block. */
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
| K_begin K_end
{ PBlock*tmp = new PBlock(PBlock::BL_SEQ);
FILE_NAME(tmp, @1);
$$ = tmp;
}
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
| K_begin statement_list K_end
{ PBlock*tmp = new PBlock(PBlock::BL_SEQ);
FILE_NAME(tmp, @1);
tmp->set_statement(*$2);
delete $2;
$$ = tmp;
}
| K_begin ':' IDENTIFIER
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ PBlock*tmp = pform_push_block_scope($3, PBlock::BL_SEQ);
FILE_NAME(tmp, @1);
current_block_stack.push(tmp);
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
}
block_item_decls_opt
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
statement_list_or_null K_end
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
{ pform_pop_scope();
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
assert(! current_block_stack.empty());
PBlock*tmp = current_block_stack.top();
current_block_stack.pop();
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
if ($6) tmp->set_statement(*$6);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$3;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
delete $6;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = tmp;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
}
| K_begin error K_end
{ yyerrok; }
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
/* fork-join blocks are very similar to begin-end blocks. In fact,
from the parser's perspective there is no real difference. All we
need to do is remember that this is a parallel block so that the
code generator can do the right thing. */
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
| K_fork K_join
{ PBlock*tmp = new PBlock(PBlock::BL_PAR);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| K_fork statement_list K_join
{ PBlock*tmp = new PBlock(PBlock::BL_PAR);
FILE_NAME(tmp, @1);
tmp->set_statement(*$2);
delete $2;
$$ = tmp;
}
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
| K_fork ':' IDENTIFIER
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
{ PBlock*tmp = pform_push_block_scope($3, PBlock::BL_PAR);
FILE_NAME(tmp, @1);
current_block_stack.push(tmp);
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
}
block_item_decls_opt
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
statement_list_or_null K_join
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
{ pform_pop_scope();
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
assert(! current_block_stack.empty());
PBlock*tmp = current_block_stack.top();
current_block_stack.pop();
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
if ($6) tmp->set_statement(*$6);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$3;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
delete $6;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = tmp;
Objects of lexical scope use PScope base class. All the pform objects that represent lexical scope now are derived from the PScope class, and are kept in a lexical_scope table so that the scope can be managed.
2008-02-16 06:20:24 +01:00
}
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
| K_fork error K_join
{ yyerrok; }
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| K_disable hierarchy_identifier ';'
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
{ PDisable*tmp = new PDisable(*$2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
delete $2;
Parse disable statements to pform.
2000-07-26 07:08:07 +02:00
$$ = tmp;
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| K_TRIGGER hierarchy_identifier ';'
Named event triggers can take hierarchical names.
2002-12-07 03:49:24 +01:00
{ PTrigger*tmp = new PTrigger(*$2);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse disable statements to pform.
2000-07-26 07:08:07 +02:00
delete $2;
Add support for procedural continuous assignment.
2000-05-12 01:37:26 +02:00
$$ = tmp;
}
Parse for declarations, implement for_step statements. for-statement declarations still generate a "sorry" message, but the for_step statements work in general now.
2012-02-25 18:28:20 +01:00
| loop_statement { $$ = $1; }
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
| K_case '(' expression ')' case_items K_endcase
Full case support
1999-09-29 20:36:02 +02:00
{ PCase*tmp = new PCase(NetCase::EQ, $3, $5);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse and elaborate the Verilog CASE statement.
1999-02-03 05:20:11 +01:00
$$ = tmp;
}
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
| K_casex '(' expression ')' case_items K_endcase
Full case support
1999-09-29 20:36:02 +02:00
{ PCase*tmp = new PCase(NetCase::EQX, $3, $5);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
$$ = tmp;
}
| K_casez '(' expression ')' case_items K_endcase
Full case support
1999-09-29 20:36:02 +02:00
{ PCase*tmp = new PCase(NetCase::EQZ, $3, $5);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Add support for the Ternary operator, Add support for repeat concatenation, Correct some seg faults cause by elaboration errors, Parse the casex anc casez statements.
1999-06-10 06:03:52 +02:00
$$ = tmp;
}
More parseable syntax.
1999-06-12 05:42:57 +02:00
| K_case '(' expression ')' error K_endcase
{ yyerrok; }
| K_casex '(' expression ')' error K_endcase
{ yyerrok; }
| K_casez '(' expression ')' error K_endcase
{ yyerrok; }
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_if '(' expression ')' statement_or_null %prec less_than_K_else
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
{ PCondit*tmp = new PCondit($3, $5, 0);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_if '(' expression ')' statement_or_null K_else statement_or_null
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
{ PCondit*tmp = new PCondit($3, $5, $7);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_if '(' error ')' statement_or_null %prec less_than_K_else
Standardize error/sorry messages.
1999-09-29 23:16:32 +02:00
{ yyerror(@1, "error: Malformed conditional expression.");
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
$$ = $5;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_if '(' error ')' statement_or_null K_else statement_or_null
Standardize error/sorry messages.
1999-09-29 23:16:32 +02:00
{ yyerror(@1, "error: Malformed conditional expression.");
Handle procedural conditional, and some of the conditional expressions. Elaborate signals and identifiers differently, allowing the netlist to hold signal information.
1998-11-07 18:05:05 +01:00
$$ = $5;
}
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
/* SytemVerilog adds the compressed_statement */
| compressed_statement ';'
{ $$ = $1; }
/* increment/decrement expressions can also be statements. When used
as statements, we can rewrite a++ as a += 1, and so on. */
| inc_or_dec_expression ';'
{ $$ = pform_compressed_assign_from_inc_dec(@1, $1); }
/* */
| delay1 statement_or_null
{ PExpr*del = $1->front();
assert($1->size() == 1);
delete $1;
PDelayStatement*tmp = new PDelayStatement(del, $2);
FILE_NAME(tmp, @1);
$$ = tmp;
}
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
| event_control attribute_list_opt statement_or_null
{ PEventStatement*tmp = $1;
if (tmp == 0) {
yyerror(@1, "error: Invalid event control.");
$$ = 0;
} else {
if ($3) pform_bind_attributes($3->attributes,$2);
tmp->set_statement($3);
$$ = tmp;
}
}
| '@' '*' attribute_list_opt statement_or_null
{ PEventStatement*tmp = new PEventStatement;
FILE_NAME(tmp, @1);
if ($4) pform_bind_attributes($4->attributes,$3);
tmp->set_statement($4);
$$ = tmp;
}
| '@' '(' '*' ')' attribute_list_opt statement_or_null
{ PEventStatement*tmp = new PEventStatement;
FILE_NAME(tmp, @1);
if ($6) pform_bind_attributes($6->attributes,$5);
tmp->set_statement($6);
$$ = tmp;
}
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
/* Various assignment statements */
Rework parse of compression assignments.
2011-11-27 20:16:39 +01:00
| lpvalue '=' expression ';'
{ PAssign*tmp = new PAssign($1,$3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
| error '=' expression ';'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@2, "Syntax in assignment statement l-value.");
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
yyerrok;
$$ = new PNoop;
}
Parse more complex continuous assign lvalues.
1999-05-07 06:26:49 +02:00
| lpvalue K_LE expression ';'
Add parse and elaboration of non-blocking assignments, Replace list<PCase::Item*> with an svector version, Add integer support.
1999-06-06 22:45:38 +02:00
{ PAssignNB*tmp = new PAssignNB($1,$3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
| error K_LE expression ';'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@2, "Syntax in assignment statement l-value.");
Allow part selects of memory words in l-values.
2006-02-02 03:43:57 +01:00
yyerrok;
$$ = new PNoop;
}
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
| lpvalue '=' delay1 expression ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ PExpr*del = $3->front(); $3->pop_front();
assert($3->empty());
Parse and elaborate rise/fall/decay times for gates, and handle the rules for partial lists of times.
1999-08-01 18:34:50 +02:00
PAssign*tmp = new PAssign($1,del,$4);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
$$ = tmp;
Parse more things.
1999-05-08 22:19:20 +02:00
}
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
| lpvalue K_LE delay1 expression ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ PExpr*del = $3->front(); $3->pop_front();
assert($3->empty());
Parse non-blocking assignment delays.
1999-09-02 03:59:27 +02:00
PAssignNB*tmp = new PAssignNB($1,del,$4);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
$$ = tmp;
}
| lpvalue '=' event_control expression ';'
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
{ PAssign*tmp = new PAssign($1,0,$3,$4);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
$$ = tmp;
}
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
| lpvalue '=' K_repeat '(' expression ')' event_control expression ';'
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
{ PAssign*tmp = new PAssign($1,$5,$7,$8);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp,@1);
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
tmp->set_lineno(@1.first_line);
$$ = tmp;
}
assignment with blocking event delay.
1999-09-22 04:00:48 +02:00
| lpvalue K_LE event_control expression ';'
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
{ PAssignNB*tmp = new PAssignNB($1,0,$3,$4);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Fix event trigger and repeat control parse errors.
1999-12-31 04:24:30 +01:00
$$ = tmp;
}
| lpvalue K_LE K_repeat '(' expression ')' event_control expression ';'
Add blocking repeat event control, make repeat sign aware This patch adds blocking repeat event controls and also makes the base repeat statement sign aware. If the argument to repeat is negative (it must be a signed variable) then this is treated just like an argument of 0 (there is no looping). Doing this allows us to model the repeat event control as follows. lhs = repeat(count) @(event) rhs; is translated to: begin temp = rhs; repeat (count) @(event); lhs = temp; end This patch also pushes the non-blocking event control information to the elaboration phase where it will report they are not currently supported.
2008-09-04 01:05:12 +02:00
{ PAssignNB*tmp = new PAssignNB($1,$5,$7,$8);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Parse non-blocking assignment delays.
1999-09-02 03:59:27 +02:00
$$ = tmp;
}
Implement increment/decrement statements. During parse/pform processing, convert increment statements to the equivalent compressed assignment statement. This is less weird for elaboration processing and better expresses what is going on.
2012-02-20 03:54:58 +01:00
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| K_wait '(' expression ')' statement_or_null
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
{ PEventStatement*tmp;
Named events really should be expressed with PEIdent objects in the pform, Handle named events within the mix of net events and edges. As a unified lot they get caught together. wait statements are broken into more complex statements that include a conditional. Do not generate NetPEvent or NetNEvent objects in elaboration. NetEvent, NetEvWait and NetEvProbe take over those functions in the netlist.
2000-04-12 06:23:57 +02:00
PEEvent*etmp = new PEEvent(PEEvent::POSITIVE, $3);
Parse OR of event expressions.
1999-04-29 04:16:26 +02:00
tmp = new PEventStatement(etmp);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp,@1);
Add procedural while loops, Parse procedural for loops, Add procedural wait statements, Add constant nodes, Add XNOR logic gate, Make vvm output look a bit prettier.
1998-11-09 19:55:33 +01:00
tmp->set_statement($5);
$$ = tmp;
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
| SYSTEM_IDENTIFIER '(' expression_list_with_nuls ')' ';'
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
{ PCallTask*tmp = new PCallTask(lex_strings.make($1), *$3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp,@1);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
delete $3;
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
| SYSTEM_IDENTIFIER ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>pt;
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
PCallTask*tmp = new PCallTask(lex_strings.make($1), pt);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp,@1);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
$$ = tmp;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '(' expression_list_proper ')' ';'
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
{ PCallTask*tmp = new PCallTask(*$1, *$3);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
delete $1;
delete $3;
$$ = tmp;
More syntax parse with sorry stubs.
1999-06-16 05:13:29 +02:00
}
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
/* NOTE: The standard doesn't really support an empty argument list
between parentheses, but it seems natural, and people commonly
want it. So accept it explicitly. */
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier '(' ')' ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>pt;
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
PCallTask*tmp = new PCallTask(*$1, pt);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Tighter parsing of statement lists and expression lists.
2007-04-02 01:02:03 +02:00
delete $1;
$$ = tmp;
}
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
| hierarchy_identifier ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>pt;
Parser and pform use hierarchical names as hname_t objects instead of encoded strings.
2001-12-03 05:47:14 +01:00
PCallTask*tmp = new PCallTask(*$1, pt);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(tmp, @1);
Elaborate user defined tasks.
1999-07-03 04:12:51 +02:00
delete $1;
$$ = tmp;
Parse more things.
1999-05-08 22:19:20 +02:00
}
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
| error ';'
Do not use the error token to get file/line number information. Using the parser supplied error token to get file and line number information appears to give incorrect results at best and core dump at worst. This patch uses the closest real token that makes sense to alleviate this problem.
2007-12-03 21:31:34 +01:00
{ yyerror(@2, "error: malformed statement");
More parseable syntax.
1999-06-12 05:42:57 +02:00
yyerrok;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
$$ = new PNoop;
}
;
Add support for C-like assignments operators SystemVerilog extended the assignments operator support to C-like assignment operators and special bitwise assignment operators. For example: a += 1; a -= 1; The list of these operators can be found in SV LRM (1800-2009) section 11.4.1. NOTE: I fixed a few parts of this. In particular, the PEBShift class is used for shift operators. Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-21 04:03:24 +02:00
compressed_statement
Rework parse of compression assignments.
2011-11-27 20:16:39 +01:00
: lpvalue K_PLUS_EQ expression
{ PAssign*tmp = new PAssign($1, '+', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_MINUS_EQ expression
{ PAssign*tmp = new PAssign($1, '-', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_MUL_EQ expression
{ PAssign*tmp = new PAssign($1, '*', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_DIV_EQ expression
{ PAssign*tmp = new PAssign($1, '/', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_MOD_EQ expression
{ PAssign*tmp = new PAssign($1, '%', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_AND_EQ expression
{ PAssign*tmp = new PAssign($1, '&', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_OR_EQ expression
{ PAssign*tmp = new PAssign($1, '|', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_XOR_EQ expression
{ PAssign*tmp = new PAssign($1, '^', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_LS_EQ expression
{ PAssign *tmp = new PAssign($1, 'l', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_RS_EQ expression
{ PAssign*tmp = new PAssign($1, 'r', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
| lpvalue K_RSS_EQ expression
{ PAssign *tmp = new PAssign($1, 'R', $3);
FILE_NAME(tmp, @1);
$$ = tmp;
}
Add support for C-like assignments operators SystemVerilog extended the assignments operator support to C-like assignment operators and special bitwise assignment operators. For example: a += 1; a -= 1; The list of these operators can be found in SV LRM (1800-2009) section 11.4.1. NOTE: I fixed a few parts of this. In particular, the PEBShift class is used for shift operators. Acked-and-Tested-by: Oswaldo Cadenas <oswaldo.cadenas@gmail.com> Signed-off-by: Prasad Joshi <prasadjoshi124@gmail.com>
2011-07-21 04:03:24 +02:00
;
Add support for a named block to only have variable definitions. It is legal for a named block to contain variable definitions and no statements. This patch fixes this for both style of blocks. It also organizes the block parsing code to be a bit more clear, adds an error case for fork/join and changes on check for size() > 0 for the more efficient ! empty().
2011-11-23 05:33:19 +01:00
statement_list_or_null
: statement_list_or_null statement
{ vector<Statement*>*tmp = $1;
if (tmp) {
tmp->push_back($2);
} else {
tmp = new vector<Statement*>(1);
tmp->at(0) = $2;
}
$$ = tmp;
}
|
{ $$ = 0; }
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
statement_list
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
: statement_list statement
{ vector<Statement*>*tmp = $1;
tmp->push_back($2);
$$ = tmp;
}
| statement
{ vector<Statement*>*tmp = new vector<Statement*>(1);
tmp->at(0) = $1;
$$ = tmp;
}
;
Introduce verilog to CVS.
1998-11-04 00:28:49 +01:00
System Verilog tasks can have multiple statements. The begin/end block that wraps the statements can be implicit.
2011-11-06 19:07:43 +01:00
statement_or_null_list
: statement_or_null_list statement_or_null
{ vector<Statement*>*tmp = $1;
tmp->push_back($2);
$$ = tmp;
}
| statement_or_null
{ vector<Statement*>*tmp = new vector<Statement*>(1);
tmp->at(0) = $1;
$$ = tmp;
}
;
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
analog_statement
: branch_probe_expression K_CONTRIBUTE expression ';'
Parse attributes on statements within event statements. Statements can have attributes attached to them. Handle a few cases in the parser where attributes may be attached to statements, and get them as far as the pform.
2008-09-05 06:27:21 +02:00
{ $$ = pform_contribution_statement(@2, $1, $3); }
Parse disciplines and contribution statements Parse discipline declarations, net discipline declarations, and analog contribution statements. Don't yet do anything useful with these, just give a sorry message where they are encountered.
2008-05-11 21:00:11 +02:00
;
Spelling fixes from Larry
2007-03-22 17:08:14 +01:00
/* Task items are, other than the statement, task port items and
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
other block items. */
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
task_item
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
: block_item_decl { $$ = new svector<PWire*>(0); }
| task_port_item { $$ = $1; }
;
task/function ports can have types.
2006-03-30 07:22:34 +02:00
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
task_port_item
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
: port_direction K_reg_opt unsigned_signed_opt range_opt list_of_identifiers ';'
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
{ svector<PWire*>*tmp = pform_make_task_ports(@1, $1,
Fix some bugs in task integer/real arguments. This patch fixes the following problem in the compiler: An integer task argument should be marked as an integer port. An implicit register can be converted to either a reg or an integer. An old style task port should default to <no type> unless reg or some other type is provided. ANSI style is always defined. For example: input ri; output ro; inout rio; real ri, ro, rio; should define all three task ports to be of type real.
2011-01-27 04:33:49 +01:00
$2 ? IVL_VT_LOGIC :
IVL_VT_NO_TYPE,
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
$3, $4, $5);
reg can take unsigned as well as signed. SystemVerilog adds "unsigned" so that it can be explicit as well as implicit.
2010-10-20 04:34:17 +02:00
$$ = tmp;
}
task/function ports can have types.
2006-03-30 07:22:34 +02:00
/* When the port is an integer, infer a signed vector of the integer
User task and function arguments can be time or realtime This patch adds the time and realtime properties for user task and function arguments. It also make a common rule for real and realtime since they are the same.
2008-08-09 03:12:52 +02:00
shape. Generate a range ([31:0]) to make it work. */
task/function ports can have types.
2006-03-30 07:22:34 +02:00
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction K_integer list_of_identifiers ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*range_stub = make_range_from_width(integer_width);
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
svector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, true,
range_stub, $3, true);
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
$$ = tmp;
}
task/function ports can have types.
2006-03-30 07:22:34 +02:00
User task and function arguments can be time or realtime This patch adds the time and realtime properties for user task and function arguments. It also make a common rule for real and realtime since they are the same.
2008-08-09 03:12:52 +02:00
/* Ports can be time with a width of [63:0] (unsigned). */
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction K_time list_of_identifiers ';'
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
{ list<PExpr*>*range_stub = make_range_from_width(64);
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
svector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_LOGIC, false,
range_stub, $3);
Remove some uses of the svector template. I'm adding more uses of the make_range_from_width function, so it seems like time to get rid of its use of the svector template. This thread led to a lot of other uses of svector that had to also be removed.
2010-10-26 04:36:44 +02:00
$$ = tmp;
}
task/function ports can have types.
2006-03-30 07:22:34 +02:00
User task and function arguments can be time or realtime This patch adds the time and realtime properties for user task and function arguments. It also make a common rule for real and realtime since they are the same.
2008-08-09 03:12:52 +02:00
/* Ports can be real or realtime. */
task/function ports can have types.
2006-03-30 07:22:34 +02:00
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
| port_direction real_or_realtime list_of_identifiers ';'
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
{ svector<PWire*>*tmp = pform_make_task_ports(@1, $1, IVL_VT_REAL, false,
0, $3);
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
$$ = tmp;
}
;
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
task_item_list
: task_item_list task_item
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
{ svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
delete $1;
delete $2;
$$ = tmp;
}
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
| task_item
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
{ $$ = $1; }
parse functions and tasks and delay value lists.
1999-05-30 05:12:56 +02:00
;
More parseable syntax.
1999-06-12 05:42:57 +02:00
task_item_list_opt
: task_item_list
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
{ $$ = $1; }
More parseable syntax.
1999-06-12 05:42:57 +02:00
|
Elaborate task input ports.
1999-07-24 04:11:19 +02:00
{ $$ = 0; }
More parseable syntax.
1999-06-12 05:42:57 +02:00
;
Add port list format for task arguments.
2006-05-11 05:26:57 +02:00
Parse array literals / rearrange task declaration rules.
2012-02-20 02:31:15 +01:00
tf_port_list_opt
: tf_port_list { $$ = $1; }
SystemVerilog has more lax rules for function declarations. Allow empty parameter lists Allow lists of statements instead of simple statements.
2011-09-17 21:10:05 +02:00
| { $$ = 0; }
;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
udp_body
: K_table { lex_start_table(); }
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
udp_entry_list
K_endtable { lex_end_table(); $$ = $3; }
;
udp_entry_list
: udp_comb_entry_list
| udp_sequ_entry_list
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
;
udp_comb_entry
: udp_input_list ':' udp_output_sym ';'
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
{ char*tmp = new char[strlen($1)+3];
strcpy(tmp, $1);
char*tp = tmp+strlen(tmp);
*tp++ = ':';
*tp++ = $3;
*tp++ = 0;
delete[]$1;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
;
udp_comb_entry_list
: udp_comb_entry
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
{ list<string>*tmp = new list<string>;
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
tmp->push_back($1);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
| udp_comb_entry_list udp_comb_entry
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
{ list<string>*tmp = $1;
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
tmp->push_back($2);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
;
udp_sequ_entry_list
: udp_sequ_entry
{ list<string>*tmp = new list<string>;
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
tmp->push_back($1);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
| udp_sequ_entry_list udp_sequ_entry
{ list<string>*tmp = $1;
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
tmp->push_back($2);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
;
udp_sequ_entry
: udp_input_list ':' udp_input_sym ':' udp_output_sym ';'
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
{ char*tmp = new char[strlen($1)+5];
strcpy(tmp, $1);
char*tp = tmp+strlen(tmp);
*tp++ = ':';
*tp++ = $3;
*tp++ = ':';
*tp++ = $5;
*tp++ = 0;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
;
udp_initial
Break sized constants into a size token and a based numeric constant.
2003-04-14 05:37:47 +02:00
: K_initial IDENTIFIER '=' number ';'
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
{ PExpr*etmp = new PENumber($4);
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
PEIdent*itmp = new PEIdent(lex_strings.make($2));
Parse and elaborate the concatenate operator in structural contexts, Replace vector<PExpr*> and list<PExpr*> with svector<PExpr*>, evaluate constant expressions with parameters, handle memories as lvalues. Parse task declarations, integer types.
1999-05-10 02:16:57 +02:00
PAssign*atmp = new PAssign(itmp, etmp);
LineInfo uses perm_string for path. Rework the handling of file names to use a perm_string heap to hold the file names, instead of the custom file name heap in the lexor. Also rename the get_line to get_fileline to reflect its real duties. This latter chage touched a lot of files.
2007-12-20 18:31:01 +01:00
FILE_NAME(atmp, @2);
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = atmp;
}
;
udp_init_opt
: udp_initial { $$ = $1; }
| { $$ = 0; }
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
;
udp_input_list
: udp_input_sym
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
{ char*tmp = new char[2];
tmp[0] = $1;
tmp[1] = 0;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
| udp_input_list udp_input_sym
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
{ char*tmp = new char[strlen($1)+2];
strcpy(tmp, $1);
char*tp = tmp+strlen(tmp);
*tp++ = $2;
*tp++ = 0;
delete[]$1;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
$$ = tmp;
}
;
udp_input_sym
: '0' { $$ = '0'; }
| '1' { $$ = '1'; }
| 'x' { $$ = 'x'; }
| '?' { $$ = '?'; }
| 'b' { $$ = 'b'; }
| '*' { $$ = '*'; }
Parse all the various edge types.
2000-03-05 19:26:51 +01:00
| '%' { $$ = '%'; }
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
| 'f' { $$ = 'f'; }
Parse all the various edge types.
2000-03-05 19:26:51 +01:00
| 'F' { $$ = 'F'; }
Add more UDP edge types, and finish up compile and run-time support. (Stephan Boettcher)
2001-06-18 02:51:23 +02:00
| 'l' { $$ = 'l'; }
Add more file/line and scope information to the ivl interface, etc. This patch adds/fixes the following: Adds file/line information to a UDP definition. Prints an error message if a UDP is passed signals wider than 1 bit. A UDP should supports a range, but the compiler currently does not. Add scope information for constants. Fix the Icarus extension UDP table entry element 'h' to use h. The ivl_udp_init() value is a char not unsigned. Add FILE_NAME() for a bunch more of the ivl interface objects.
2011-02-07 04:47:11 +01:00
| 'h' { $$ = 'h'; }
Add more UDP edge types, and finish up compile and run-time support. (Stephan Boettcher)
2001-06-18 02:51:23 +02:00
| 'B' { $$ = 'B'; }
Fully elaborate Sequential UDP behavior.
1998-12-14 03:01:34 +01:00
| 'r' { $$ = 'r'; }
Parse all the various edge types.
2000-03-05 19:26:51 +01:00
| 'R' { $$ = 'R'; }
Add more UDP edge types, and finish up compile and run-time support. (Stephan Boettcher)
2001-06-18 02:51:23 +02:00
| 'M' { $$ = 'M'; }
Parse more UDP input edge descriptions.
1998-12-18 06:16:25 +01:00
| 'n' { $$ = 'n'; }
Parse all the various edge types.
2000-03-05 19:26:51 +01:00
| 'N' { $$ = 'N'; }
Parse more UDP input edge descriptions.
1998-12-18 06:16:25 +01:00
| 'p' { $$ = 'p'; }
Parse all the various edge types.
2000-03-05 19:26:51 +01:00
| 'P' { $$ = 'P'; }
Add more UDP edge types, and finish up compile and run-time support. (Stephan Boettcher)
2001-06-18 02:51:23 +02:00
| 'Q' { $$ = 'Q'; }
Add bx support for udps.
2003-03-18 02:36:14 +01:00
| 'q' { $$ = 'q'; }
Parse more UDP input edge descriptions.
1998-12-18 06:16:25 +01:00
| '_' { $$ = '_'; }
Parse all the various edge types.
2000-03-05 19:26:51 +01:00
| '+' { $$ = '+'; }
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
udp_output_sym
: '0' { $$ = '0'; }
| '1' { $$ = '1'; }
| 'x' { $$ = 'x'; }
| '-' { $$ = '-'; }
;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
/* Port declarations create wires for the inputs and the output. The
makes for these ports are scoped within the UDP, so there is no
Spelling fixes mostly comments, but includes some identifiers and message text
2008-01-25 22:34:51 +01:00
hierarchy involved. */
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
udp_port_decl
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
: K_input list_of_identifiers ';'
{ $$ = pform_make_udp_input_ports($2); }
| K_output IDENTIFIER ';'
{ perm_string pname = lex_strings.make($2);
PWire*pp = new PWire(pname, NetNet::IMPLICIT, NetNet::POUTPUT, IVL_VT_LOGIC);
svector<PWire*>*tmp = new svector<PWire*>(1);
(*tmp)[0] = pp;
$$ = tmp;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
}
| K_reg IDENTIFIER ';'
{ perm_string pname = lex_strings.make($2);
PWire*pp = new PWire(pname, NetNet::REG, NetNet::PIMPLICIT, IVL_VT_LOGIC);
svector<PWire*>*tmp = new svector<PWire*>(1);
(*tmp)[0] = pp;
$$ = tmp;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$2;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
}
| K_reg K_output IDENTIFIER ';'
{ perm_string pname = lex_strings.make($3);
PWire*pp = new PWire(pname, NetNet::REG, NetNet::POUTPUT, IVL_VT_LOGIC);
svector<PWire*>*tmp = new svector<PWire*>(1);
(*tmp)[0] = pp;
$$ = tmp;
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$3;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
}
Rework the heirarchical identifier parse syntax and pform to handle more general combinations of heirarch and bit selects.
2007-05-24 06:07:11 +02:00
;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
udp_port_decls
: udp_port_decl
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
{ $$ = $1; }
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
| udp_port_decls udp_port_decl
parse more verilog.
1999-06-12 22:35:27 +02:00
{ svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
delete $1;
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
delete $2;
$$ = tmp;
}
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
;
udp_port_list
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
: IDENTIFIER
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($1));
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$1;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = tmp;
}
| udp_port_list ',' IDENTIFIER
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($3));
Fix malloc/free and new/delete problems, plus some initializations. This patch fixes some allocation problems (mostly in the parser and lexor relating to identifiers). It also fixes a couple places where uninitialized variables were used. All found with valgrind. There are still 100 tests that have problems. Many of these appear to be related.
2008-03-28 04:30:53 +01:00
delete[]$3;
Rework handling of lexical scope Move the storage of wires (signals) out of the Module class into the PScope base class, and instead of putting the PWires all into the Module object, distribute them into the various lexical scopes (derived from PScope) so that the wire names do not need to carry scope information. This required some rewiring of elaboration of signals, and rewriting of lexical scope handling.
2008-02-25 04:40:54 +01:00
$$ = tmp;
}
;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
udp_reg_opt: K_reg { $$ = true; } | { $$ = false; };
udp_initial_expr_opt
: '=' expression { $$ = $2; }
| { $$ = 0; }
;
udp_input_declaration_list
: K_input IDENTIFIER
{ list<perm_string>*tmp = new list<perm_string>;
tmp->push_back(lex_strings.make($2));
$$ = tmp;
delete[]$2;
}
| udp_input_declaration_list ',' K_input IDENTIFIER
{ list<perm_string>*tmp = $1;
tmp->push_back(lex_strings.make($4));
$$ = tmp;
delete[]$4;
}
;
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
udp_primitive
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
/* This is the syntax for primitives that uses the IEEE1364-1995
format. The ports are simply names in the port list, and the
declarations are in the body. */
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
: K_primitive IDENTIFIER '(' udp_port_list ')' ';'
udp_port_decls
Parse UDP primitives all the way to pform.
1998-11-25 03:35:53 +01:00
udp_init_opt
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
udp_body
K_endprimitive
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
Use perm_strings for named langiage items.
2004-02-18 18:11:54 +01:00
{ perm_string tmp2 = lex_strings.make($2);
pform_make_udp(tmp2, $4, $7, $9, $8,
Error messages for missing UDP port declarations.
2001-10-21 03:55:24 +02:00
@2.text, @2.first_line);
remove string from lexical phase.
1999-07-10 03:03:18 +02:00
delete[]$2;
}
Verilog2001 new style port declartions for primitives.
2004-03-08 01:10:29 +01:00
/* This is the syntax for IEEE1364-2001 format definitions. The port
names and declarations are all in the parameter list. */
| K_primitive IDENTIFIER
'(' K_output udp_reg_opt IDENTIFIER udp_initial_expr_opt ','
udp_input_declaration_list ')' ';'
udp_body
K_endprimitive
{ perm_string tmp2 = lex_strings.make($2);
perm_string tmp6 = lex_strings.make($6);
pform_make_udp(tmp2, $5, tmp6, $7, $9, $12,
@2.text, @2.first_line);
delete[]$2;
delete[]$6;
}
NetAssign handles lvalues as pin links instead of a signal pointer, Wire attributes added, Ability to parse UDP descriptions added, XNF generates EXT records for signals with the PAD attribute.
1998-11-23 01:20:22 +01:00
;
Parse support for struct variables.
2011-12-04 02:16:01 +01:00
More class syntax Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 19:29:50 +01:00
/* Many keywords can be optional in the syntax, although their
presence is significant. This is a fairly common pattern so
collect those rules here. */
K_automatic_opt: K_automatic { $$ = true; } | { $$ = false;} ;
K_packed_opt : K_packed { $$ = true; } | { $$ = false; } ;
K_reg_opt : K_reg { $$ = true; } | { $$ = false; } ;
K_virtual_opt : K_virtual { $$ = true; } | { $$ = false; } ;