Full case support
This commit is contained in:
parent
3a415fb04c
commit
a64a33e65a
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: Statement.cc,v 1.15 1999/09/22 02:00:48 steve Exp $"
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#ident "$Id: Statement.cc,v 1.16 1999/09/29 18:36:02 steve Exp $"
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#endif
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# include "Statement.h"
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@ -108,8 +108,8 @@ PCallTask::PCallTask(const string&n, const svector<PExpr*>&p)
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{
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}
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PCase::PCase(PExpr*ex, svector<PCase::Item*>*l)
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: expr_(ex), items_(l)
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PCase::PCase(NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
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: type_(t), expr_(ex), items_(l)
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{
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}
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@ -163,6 +163,9 @@ PWhile::~PWhile()
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/*
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* $Log: Statement.cc,v $
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* Revision 1.16 1999/09/29 18:36:02 steve
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* Full case support
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*
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* Revision 1.15 1999/09/22 02:00:48 steve
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* assignment with blocking event delay.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: Statement.h,v 1.19 1999/09/22 02:00:48 steve Exp $"
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#ident "$Id: Statement.h,v 1.20 1999/09/29 18:36:02 steve Exp $"
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#endif
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# include <string>
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@ -200,13 +200,14 @@ class PCase : public Statement {
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Statement*stat;
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};
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PCase(PExpr*ex, svector<Item*>*);
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PCase(NetCase::TYPE, PExpr*ex, svector<Item*>*);
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~PCase();
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virtual NetProc* elaborate(Design*des, const string&path) const;
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virtual void dump(ostream&out, unsigned ind) const;
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private:
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NetCase::TYPE type_;
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PExpr*expr_;
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svector<Item*>*items_;
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@ -346,6 +347,9 @@ class PWhile : public Statement {
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/*
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* $Log: Statement.h,v $
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* Revision 1.20 1999/09/29 18:36:02 steve
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* Full case support
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*
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* Revision 1.19 1999/09/22 02:00:48 steve
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* assignment with blocking event delay.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: design_dump.cc,v 1.43 1999/09/21 00:13:40 steve Exp $"
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#ident "$Id: design_dump.cc,v 1.44 1999/09/29 18:36:03 steve Exp $"
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#endif
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/*
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@ -406,7 +406,14 @@ void NetBlock::dump(ostream&o, unsigned ind) const
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void NetCase::dump(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "case (" << *expr_ << ")" << endl;
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switch (type_) {
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case EQ:
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o << setw(ind) << "" << "case (" << *expr_ << ")" << endl;
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case EQX:
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o << setw(ind) << "" << "casex (" << *expr_ << ")" << endl;
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case EQZ:
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o << setw(ind) << "" << "casez (" << *expr_ << ")" << endl;
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}
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for (unsigned idx = 0 ; idx < nitems_ ; idx += 1) {
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o << setw(ind+2) << "";
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@ -761,6 +768,9 @@ void Design::dump(ostream&o) const
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/*
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* $Log: design_dump.cc,v $
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* Revision 1.44 1999/09/29 18:36:03 steve
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* Full case support
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*
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* Revision 1.43 1999/09/21 00:13:40 steve
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* Support parameters that reference other paramters.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.101 1999/09/29 00:42:50 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.102 1999/09/29 18:36:03 steve Exp $"
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#endif
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/*
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@ -1845,7 +1845,8 @@ NetProc* PCase::elaborate(Design*des, const string&path) const
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icount += cur->expr.count();
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}
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NetCase*res = new NetCase(expr, icount);
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NetCase*res = new NetCase(type_, expr, icount);
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res->set_line(*this);
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unsigned inum = 0;
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for (unsigned idx = 0 ; idx < items_->count() ; idx += 1) {
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@ -2572,6 +2573,9 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.102 1999/09/29 18:36:03 steve
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* Full case support
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*
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* Revision 1.101 1999/09/29 00:42:50 steve
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* Allow expanding of additive operators.
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*
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19
netlist.cc
19
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.cc,v 1.70 1999/09/28 03:11:29 steve Exp $"
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#ident "$Id: netlist.cc,v 1.71 1999/09/29 18:36:03 steve Exp $"
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#endif
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# include <cassert>
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@ -292,6 +292,11 @@ unsigned NetNet::sb_to_idx(long sb) const
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return lsb_ - sb;
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}
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NetProc::NetProc()
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: next_(0)
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{
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}
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NetProc::~NetProc()
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{
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}
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@ -511,8 +516,8 @@ void NetBlock::append(NetProc*cur)
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}
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}
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NetCase::NetCase(NetExpr*ex, unsigned cnt)
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: expr_(ex), nitems_(cnt)
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NetCase::NetCase(NetCase::TYPE c, NetExpr*ex, unsigned cnt)
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: type_(c), expr_(ex), nitems_(cnt)
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{
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assert(expr_);
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items_ = new Item[nitems_];
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@ -531,6 +536,11 @@ NetCase::~NetCase()
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delete[]items_;
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}
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NetCase::TYPE NetCase::type() const
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{
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return type_;
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}
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void NetCase::set_case(unsigned idx, NetExpr*e, NetProc*p)
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{
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assert(idx < nitems_);
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@ -1647,6 +1657,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
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/*
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* $Log: netlist.cc,v $
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* Revision 1.71 1999/09/29 18:36:03 steve
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* Full case support
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*
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* Revision 1.70 1999/09/28 03:11:29 steve
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* Get the bit widths of unary operators that return one bit.
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*
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34
netlist.h
34
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.73 1999/09/28 03:11:30 steve Exp $"
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#ident "$Id: netlist.h,v 1.74 1999/09/29 18:36:03 steve Exp $"
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#endif
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/*
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@ -583,10 +583,10 @@ class NetUDP : public NetNode {
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* linked into the netlist. However, elaborating a process may cause
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* special nodes to be created to handle things like events.
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*/
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class NetProc {
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class NetProc : public LineInfo {
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public:
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explicit NetProc() : next_(0) { }
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explicit NetProc();
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virtual ~NetProc();
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// This method is called to emit the statement to the
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@ -613,7 +613,7 @@ class NetProc {
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* should know that this is not a guarantee.
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*/
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class NetAssign_ : public NetProc, public NetNode, public LineInfo {
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class NetAssign_ : public NetProc, public NetNode {
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protected:
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NetAssign_(const string&n, unsigned w);
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@ -675,7 +675,7 @@ class NetAssignNB : public NetAssign_ {
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* regular assign, and the NetAssignMem_ base class takes care of all
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* the common stuff.
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*/
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class NetAssignMem_ : public NetProc, public LineInfo {
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class NetAssignMem_ : public NetProc {
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public:
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explicit NetAssignMem_(NetMemory*, NetExpr*idx, NetExpr*rv);
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@ -743,18 +743,27 @@ class NetBlock : public NetProc {
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NetProc*last_;
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};
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/* A CASE statement in the verilog source leads, eventually, to one of
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these. This is different from a simple conditional because of the
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way the comparisons are performed. Also, it is likely that the
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target may be able to optimize differently. */
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/*
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* A CASE statement in the verilog source leads, eventually, to one of
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* these. This is different from a simple conditional because of the
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* way the comparisons are performed. Also, it is likely that the
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* target may be able to optimize differently.
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*
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* Case cane be one of three types:
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* EQ -- All bits must exactly match
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* EQZ -- z bits are don't care
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* EQX -- x and z bits are don't care.
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*/
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class NetCase : public NetProc {
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public:
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NetCase(NetExpr*ex, unsigned cnt);
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enum TYPE { EQ, EQX, EQZ };
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NetCase(TYPE c, NetExpr*ex, unsigned cnt);
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~NetCase();
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void set_case(unsigned idx, NetExpr*ex, NetProc*st);
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TYPE type() const;
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const NetExpr*expr() const { return expr_; }
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unsigned nitems() const { return nitems_; }
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@ -766,6 +775,8 @@ class NetCase : public NetProc {
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private:
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TYPE type_;
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struct Item {
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NetExpr*guard;
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NetProc*statement;
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@ -1689,6 +1700,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.74 1999/09/29 18:36:03 steve
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* Full case support
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*
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* Revision 1.73 1999/09/28 03:11:30 steve
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* Get the bit widths of unary operators that return one bit.
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*
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10
parse.y
10
parse.y
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: parse.y,v 1.67 1999/09/25 02:57:30 steve Exp $"
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#ident "$Id: parse.y,v 1.68 1999/09/29 18:36:04 steve Exp $"
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#endif
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# include "parse_misc.h"
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@ -1490,23 +1490,21 @@ statement
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$$ = tmp;
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}
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| K_case '(' expression ')' case_items K_endcase
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{ PCase*tmp = new PCase($3, $5);
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{ PCase*tmp = new PCase(NetCase::EQ, $3, $5);
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tmp->set_file(@1.text);
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tmp->set_lineno(@1.first_line);
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$$ = tmp;
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}
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| K_casex '(' expression ')' case_items K_endcase
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{ PCase*tmp = new PCase($3, $5);
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{ PCase*tmp = new PCase(NetCase::EQX, $3, $5);
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tmp->set_file(@1.text);
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tmp->set_lineno(@1.first_line);
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yywarn(@1, "casex not properly supported, using case.");
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$$ = tmp;
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}
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| K_casez '(' expression ')' case_items K_endcase
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{ PCase*tmp = new PCase($3, $5);
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{ PCase*tmp = new PCase(NetCase::EQZ, $3, $5);
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tmp->set_file(@1.text);
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tmp->set_lineno(@1.first_line);
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yywarn(@1, "casez not properly supported, using case.");
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$$ = tmp;
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}
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| K_case '(' expression ')' error K_endcase
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: pform_dump.cc,v 1.39 1999/09/17 02:06:26 steve Exp $"
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#ident "$Id: pform_dump.cc,v 1.40 1999/09/29 18:36:04 steve Exp $"
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#endif
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/*
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@ -361,8 +361,19 @@ void PCallTask::dump(ostream&out, unsigned ind) const
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void PCase::dump(ostream&out, unsigned ind) const
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{
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out << setw(ind) << "" << "case (" << *expr_ << ") /* " <<
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get_line() << " */" << endl;
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out << setw(ind) << "";
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switch (type_) {
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case NetCase::EQ:
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out << "case";
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break;
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case NetCase::EQX:
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out << "casex";
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break;
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case NetCase::EQZ:
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out << "casez";
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break;
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}
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out << " (" << *expr_ << ") /* " << get_line() << " */" << endl;
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for (unsigned idx = 0 ; idx < items_->count() ; idx += 1) {
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PCase::Item*cur = (*items_)[idx];
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@ -645,6 +656,9 @@ void PUdp::dump(ostream&out) const
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/*
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* $Log: pform_dump.cc,v $
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* Revision 1.40 1999/09/29 18:36:04 steve
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* Full case support
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*
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* Revision 1.39 1999/09/17 02:06:26 steve
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* Handle unconnected module ports.
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*
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22
t-vvm.cc
22
t-vvm.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-vvm.cc,v 1.51 1999/09/29 00:42:25 steve Exp $"
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#ident "$Id: t-vvm.cc,v 1.52 1999/09/29 18:36:04 steve Exp $"
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#endif
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# include <iostream>
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@ -1198,6 +1198,19 @@ bool target_vvm::proc_block(ostream&os, const NetBlock*net)
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*/
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void target_vvm::proc_case(ostream&os, const NetCase*net)
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{
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string test_func = "";
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switch (net->type()) {
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case NetCase::EQ:
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test_func = "vvm_binop_eeq";
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break;
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case NetCase::EQX:
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test_func = "vvm_binop_xeq";
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break;
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case NetCase::EQZ:
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test_func = "vvm_binop_zeq";
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break;
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}
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os << " /* case (" << *net->expr() << ") */" << endl;
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string expr = emit_proc_rval(os, 8, net->expr());
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@ -1223,8 +1236,8 @@ void target_vvm::proc_case(ostream&os, const NetCase*net)
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thread_step_ += 1;
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os << " if (" << expr << ".eequal(" << guard <<
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")) {" << endl;
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os << " if (V1 == " << test_func << "(" << guard << ","
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<< expr << ")[0]) {" << endl;
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os << " step_ = &" << thread_class_ <<
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"::step_" << thread_step_ << "_;" << endl;
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os << " return true;" << endl;
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@ -1563,6 +1576,9 @@ extern const struct target tgt_vvm = {
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};
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/*
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* $Log: t-vvm.cc,v $
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* Revision 1.52 1999/09/29 18:36:04 steve
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* Full case support
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*
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* Revision 1.51 1999/09/29 00:42:25 steve
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* Comment on where binary operator came from.
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*
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12
vvm/vvm.h
12
vvm/vvm.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm.h,v 1.11 1999/09/28 01:13:15 steve Exp $"
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#ident "$Id: vvm.h,v 1.12 1999/09/29 18:36:04 steve Exp $"
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#endif
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# include <vector>
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@ -133,13 +133,6 @@ template <unsigned WIDTH> class vvm_bitset_t : public vvm_bits_t {
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unsigned get_width() const { return WIDTH; }
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vvm_bit_t get_bit(unsigned idx) const { return bits_[idx]; }
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bool eequal(const vvm_bitset_t<WIDTH>&that) const
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{ for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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if (bits_[idx] != that.bits_[idx])
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return false;
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return true;
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}
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unsigned as_unsigned() const
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{ unsigned result = 0;
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for (unsigned idx = WIDTH ; idx > 0 ; idx -= 1) {
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@ -289,6 +282,9 @@ template <unsigned WIDTH> class vvm_signal_t : public vvm_monitor_t {
|
|||
|
||||
/*
|
||||
* $Log: vvm.h,v $
|
||||
* Revision 1.12 1999/09/29 18:36:04 steve
|
||||
* Full case support
|
||||
*
|
||||
* Revision 1.11 1999/09/28 01:13:15 steve
|
||||
* Support in vvm > and >= behavioral operators.
|
||||
*
|
||||
|
|
|
|||
115
vvm/vvm_func.h
115
vvm/vvm_func.h
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: vvm_func.h,v 1.10 1999/09/28 01:13:16 steve Exp $"
|
||||
#ident "$Id: vvm_func.h,v 1.11 1999/09/29 18:36:04 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "vvm.h"
|
||||
|
|
@ -239,6 +239,10 @@ vvm_bitset_t<1> vvm_binop_eq(const vvm_bitset_t<LW>&l,
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This function return true if all the bits are the same. Even x and
|
||||
* z bites are compared for equality.
|
||||
*/
|
||||
template <unsigned LW, unsigned RW>
|
||||
vvm_bitset_t<1> vvm_binop_eeq(const vvm_bitset_t<LW>&l,
|
||||
const vvm_bitset_t<RW>&r)
|
||||
|
|
@ -277,6 +281,112 @@ vvm_bitset_t<1> vvm_binop_eeq(const vvm_bitset_t<LW>&l,
|
|||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function return true if all the bits are the same. The x and z
|
||||
* bits are don't care, s don't make the result false.
|
||||
*/
|
||||
template <unsigned LW, unsigned RW>
|
||||
vvm_bitset_t<1> vvm_binop_xeq(const vvm_bitset_t<LW>&l,
|
||||
const vvm_bitset_t<RW>&r)
|
||||
{
|
||||
vvm_bitset_t<1> result;
|
||||
result[0] = V1;
|
||||
|
||||
if (LW <= RW) {
|
||||
for (unsigned idx = 0 ; idx < LW ; idx += 1) {
|
||||
if ((l[idx] == Vz) || (r[idx] == Vz))
|
||||
continue;
|
||||
if ((l[idx] == Vx) || (r[idx] == Vx))
|
||||
continue;
|
||||
if (l[idx] != r[idx]) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
for (unsigned idx = LW ; idx < RW ; idx += 1) {
|
||||
if ((r[idx] == Vx) || (r[idx] == Vz))
|
||||
continue;
|
||||
if (r[idx] != V0) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
|
||||
} else {
|
||||
for (unsigned idx = 0 ; idx < RW ; idx += 1) {
|
||||
if ((l[idx] == Vz) || (r[idx] == Vz))
|
||||
continue;
|
||||
if ((l[idx] == Vx) || (r[idx] == Vx))
|
||||
continue;
|
||||
if (l[idx] != r[idx]) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
for (unsigned idx = RW ; idx < LW ; idx += 1) {
|
||||
if ((l[idx] == Vx) || (l[idx] == Vz))
|
||||
continue;
|
||||
if (l[idx] != V0) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function return true if all the bits are the same. The z
|
||||
* bits are don't care, so don't make the result false.
|
||||
*/
|
||||
template <unsigned LW, unsigned RW>
|
||||
vvm_bitset_t<1> vvm_binop_zeq(const vvm_bitset_t<LW>&l,
|
||||
const vvm_bitset_t<RW>&r)
|
||||
{
|
||||
vvm_bitset_t<1> result;
|
||||
result[0] = V1;
|
||||
|
||||
if (LW <= RW) {
|
||||
for (unsigned idx = 0 ; idx < LW ; idx += 1) {
|
||||
if ((l[idx] == Vz) || (r[idx] == Vz))
|
||||
continue;
|
||||
if (l[idx] != r[idx]) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
for (unsigned idx = LW ; idx < RW ; idx += 1) {
|
||||
if (r[idx] == Vz)
|
||||
continue;
|
||||
if (r[idx] != V0) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
|
||||
} else {
|
||||
for (unsigned idx = 0 ; idx < RW ; idx += 1) {
|
||||
if ((l[idx] == Vz) || (r[idx] == Vz))
|
||||
continue;
|
||||
if (l[idx] != r[idx]) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
for (unsigned idx = RW ; idx < LW ; idx += 1) {
|
||||
if (l[idx] == Vz)
|
||||
continue;
|
||||
if (l[idx] != V0) {
|
||||
result[0] = V0;
|
||||
return result;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
template <unsigned LW, unsigned RW>
|
||||
vvm_bitset_t<1> vvm_binop_ne(const vvm_bitset_t<LW>&l,
|
||||
const vvm_bitset_t<RW>&r)
|
||||
|
|
@ -411,6 +521,9 @@ vvm_bitset_t<W> vvm_ternary(vvm_bit_t c, const vvm_bitset_t<W>&t,
|
|||
|
||||
/*
|
||||
* $Log: vvm_func.h,v $
|
||||
* Revision 1.11 1999/09/29 18:36:04 steve
|
||||
* Full case support
|
||||
*
|
||||
* Revision 1.10 1999/09/28 01:13:16 steve
|
||||
* Support in vvm > and >= behavioral operators.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue