parse drive strengths.
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@ -327,6 +327,8 @@ current state of support for Verilog.
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reg [7:0] del;
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always #(reg) $display($time,,"del = %d", del); // sorry
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- drive strengths are parsed, bug ignored.
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Specify blocks are parsed but ignored in general.
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23
parse.y
23
parse.y
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: parse.y,v 1.74 1999/10/15 05:03:33 steve Exp $"
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#ident "$Id: parse.y,v 1.75 1999/11/05 19:36:36 steve Exp $"
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#endif
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# include "parse_misc.h"
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@ -336,6 +336,23 @@ description
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}
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;
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drive_strength
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: '(' dr_strength0 ',' dr_strength1 ')'
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| '(' dr_strength1 ',' dr_strength0 ')'
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| '(' dr_strength0 ',' K_highz1 ')'
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| '(' dr_strength1 ',' K_highz0 ')'
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| '(' K_highz1 ',' dr_strength0 ')'
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| '(' K_highz0 ',' dr_strength1 ')'
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;
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drive_strength_opt
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: drive_strength
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;
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dr_strength0 : K_supply0 | K_strong0 | K_pull0 | K_weak0 ;
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dr_strength1 : K_supply1 | K_strong1 | K_pull1 | K_weak1 ;
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event_control
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: '@' IDENTIFIER
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{ yyerror(@1, "sorry: event control not supported.");
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@ -1061,8 +1078,8 @@ module_item
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{ pform_make_modgates($1, $2, $3);
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delete $1;
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}
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| K_assign delay_opt assign_list ';'
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{ pform_make_pgassign_list($3, $2, @1.text, @1.first_line); }
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| K_assign drive_strength_opt delay_opt assign_list ';'
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{ pform_make_pgassign_list($4, $3, @1.text, @1.first_line); }
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| K_assign error '=' expression ';'
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| K_always statement
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{ PProcess*tmp = pform_make_behavior(PProcess::PR_ALWAYS, $2);
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