Commit Graph

438 Commits

Author SHA1 Message Date
AngeloJacobo b02e66b7d8 revert changes in shiftin and iodelay_group string name since openxc7 now works on them 2025-03-16 12:29:48 +08:00
AngeloJacobo 0175db1ca6 openFPGAloader now working on qmtech_wukong 2025-03-14 16:12:25 +08:00
AngeloJacobo 58f887ced3 openfpgaloader now works on qmtech_kintex7 2025-03-14 16:03:18 +08:00
AngeloJacobo 5ab1ac5d42 add UART to ax7325b board, make openFPGAloader works on ax7325b board 2025-03-14 15:23:34 +08:00
AngeloJacobo 75e42476f5 openfpgaloader now working on alinx ax7103b board 2025-03-14 14:34:25 +08:00
AngeloJacobo 117a9c5837 update enclustra demo project 2025-03-14 13:56:24 +08:00
AngeloJacobo d787c77116 pass simulation 2025-03-13 18:31:23 +08:00
AngeloJacobo 89568b127c add demo project for qmtech kintex-7 board 2025-03-09 10:41:33 +08:00
AngeloJacobo 7f801b1f1d add uart_tx to top 2025-03-02 19:05:30 +08:00
AngeloJacobo c0bc4ca48a removed extra semicolon 2025-03-02 18:46:07 +08:00
AngeloJacobo 4ce06f5fd8 all example demos passing openxc7 run! 2025-03-02 18:42:49 +08:00
AngeloJacobo e8444fb379 fix flagged errors from openxc7 (shiftin grounded, iodelay_group string) 2025-03-02 18:40:18 +08:00
AngeloJacobo 0c484d54f6 fix flagged errors from openxc7 2025-03-02 14:34:59 +08:00
AngeloJacobo 94b4e0866b added UART for debugging, DQ now support 1 cycle late 2025-03-02 14:15:44 +08:00
AngeloJacobo 5c52351bce uncommented default_nettype 2025-03-01 19:32:35 +08:00
AngeloJacobo e19c6023c4 remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing 2025-03-01 15:51:48 +08:00
AngeloJacobo 4a71002cf8 ignore new fiels due to new verilator, run_compile can now run lint separately 2025-03-01 14:42:05 +08:00
AngeloJacobo 99eaa7d103 added IODELAY_GROUP for ODELAY,IDELAY,and IDELAYCTRL 2025-03-01 14:41:00 +08:00
AngeloJacobo 74f68760a4 removed mark_debug 2025-03-01 14:40:21 +08:00
AngeloJacobo f10fc7d10b vivado simulation files directory are now relative, can now run sim anywhere 2025-03-01 14:39:54 +08:00
AngeloJacobo af48f1fa08 solve timing slack due to 64-bit counters 2025-02-27 20:28:55 +08:00
Angelo Jacobo c0e3f32bfb
Merge pull request #22 from AngeloJacobo/higher_speed_feature
Pass simulation and hardware test for DDR3-1333 and DDR3-1600!
2025-02-22 11:32:19 +08:00
Angelo Jacobo 3898b1e762
Merge branch 'main' into higher_speed_feature 2025-02-22 11:31:54 +08:00
AngeloJacobo 1db41ad9e1 add xdc for microblaze run, and minor fixes in params 2025-02-22 11:23:24 +08:00
AngeloJacobo d6f50b3a6a update UberDDR3 AXI for Vivado custom IP 2025-02-16 14:53:05 +08:00
AngeloJacobo 48fd64588b update to ddr3-1333 2025-02-13 19:32:19 +08:00
AngeloJacobo c21b8a0a37 uberddr3 test on enclustra board, with MicroBlaze for summary reporting via UART 2025-02-13 19:27:11 +08:00
AngeloJacobo d4ecfee105 improve latency of ack after write 2025-02-09 16:16:42 +08:00
AngeloJacobo 97424583ba formal all passing 2025-02-09 09:52:29 +08:00
AngeloJacobo 7ada4bcbab add support for BIST_MODE = 0,1,and 2 , write data is also randomized 2025-02-09 09:48:46 +08:00
AngeloJacobo 058da90bfc changed SKIP_INTERNAL_TEST to BIST_MODE (0,1, or 2) 2025-02-09 09:45:30 +08:00
AngeloJacobo 016df010c7 added regression test shell scrip to simulate multiple corners 2025-01-30 19:16:11 +08:00
AngeloJacobo c81f9044d8 add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600! 2025-01-30 19:07:09 +08:00
AngeloJacobo 760979db27 hardware runs on ddr3-1333! Now working on ddr3-1600 2025-01-19 17:15:40 +08:00
Angelo Jacobo faa94a839a
Merge pull request #21 from AngeloJacobo/uberddr3_with_xadc
Added simulation and project demo with XADC
2025-01-18 14:15:10 +08:00
AngeloJacobo 339adfe8d6 added simulation and project demo with XADC 2025-01-12 14:55:43 +08:00
Angelo Jacobo ae3cb666e6
Merge pull request #20 from AngeloJacobo/spd_reader
SPD reader for DDR3 DIMM
2025-01-11 14:18:26 +08:00
Angelo Jacobo 6cf9dc08f6
add new parameters, and links for OpenIPHub blog posts 2025-01-03 11:29:09 +08:00
Angelo Jacobo 60dce3f0fa
Merge pull request #19 from AngeloJacobo/dual_rank_feature
Add support for dual rank
2025-01-03 09:35:20 +08:00
AngeloJacobo d8cb6d16d9 update copyright date 2025-01-02 13:18:42 +08:00
AngeloJacobo fbb3b65aaf added waveform for spd reader testbench 2025-01-02 13:02:05 +08:00
AngeloJacobo c11d90440e fixed mtb computation 2024-12-29 22:11:26 +08:00
AngeloJacobo 1afd06542f make mtb mcp to meet timing 2024-12-29 21:58:26 +08:00
AngeloJacobo ab1a5b9f81 make spd read display better 2024-12-29 21:40:53 +08:00
AngeloJacobo 6ead81ba48 fixed stuck on addr 21, and fixed dual rank 2024-12-29 21:33:58 +08:00
AngeloJacobo f636dcbd2e bring all timing parameters to top 2024-12-29 21:22:52 +08:00
AngeloJacobo d424bcdf4e add option to debug all registers in ILA 2024-12-29 20:59:57 +08:00
AngeloJacobo 7acaf34b44 added uart to display spd report 2024-12-29 20:41:17 +08:00
AngeloJacobo 253d9495ca added led to xdc 2024-12-29 14:53:19 +08:00
AngeloJacobo 75857a0af0 read bytes 0 to 63 of spd then store (sim passing) 2024-12-29 14:47:57 +08:00