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changed SKIP_INTERNAL_TEST to BIST_MODE (0,1, or 2)

This commit is contained in:
AngeloJacobo 2025-02-09 09:45:30 +08:00
parent 016df010c7
commit 058da90bfc
9 changed files with 54156 additions and 44290 deletions
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2
rtl/ddr3_phy.v
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@ -28,7 +28,7 @@
//
////////////////////////////////////////////////////////////////////////////////
`default_nettype none
// `default_nettype none
`timescale 1ps / 1ps
//`define DEBUG_DQS // uncomment to route the raw DQS to output port for debugging

54
rtl/ddr3_top.v
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@ -27,7 +27,7 @@
//
////////////////////////////////////////////////////////////////////////////////
`default_nettype none
//`default_nettype none
`timescale 1ps / 1ps
module ddr3_top #(
@ -51,7 +51,7 @@ module ddr3_top #(
ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed
WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
SKIP_INTERNAL_TEST = 0, // skip built-in self test (would require >2 seconds of internal test right after calibration)
parameter[1:0] BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing)
@ -259,7 +259,7 @@ ddr3_top #(
.SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
.RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
.DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 = enable, 0 = disable)
@ -386,29 +386,29 @@ ddr3_top #(
.o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
);
// display value of parameters for easy debugging
initial begin
$display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
$display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
$display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
$display("ROW_BITS = %0d", ROW_BITS);
$display("COL_BITS = %0d", COL_BITS);
$display("BA_BITS = %0d", BA_BITS);
$display("BYTE_LANES = %0d", BYTE_LANES);
$display("AUX_WIDTH = %0d", AUX_WIDTH);
$display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
$display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
$display("MICRON_SIM = %0d", MICRON_SIM);
$display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
$display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
$display("WB_ERROR = %0d", WB_ERROR);
$display("SKIP_INTERNAL_TEST = %0d", SKIP_INTERNAL_TEST);
$display("ECC_ENABLE = %0d", ECC_ENABLE);
$display("DIC = %0d", DIC);
$display("RTT_NOM = %0d", RTT_NOM);
$display("SELF_REFRESH = %0d", SELF_REFRESH);
$display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
$display("End of DDR3 TOP PARAMETERS\n-----------------------------");
end
// // display value of parameters for easy debugging
// initial begin
// $display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
// $display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
// $display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
// $display("ROW_BITS = %0d", ROW_BITS);
// $display("COL_BITS = %0d", COL_BITS);
// $display("BA_BITS = %0d", BA_BITS);
// $display("BYTE_LANES = %0d", BYTE_LANES);
// $display("AUX_WIDTH = %0d", AUX_WIDTH);
// $display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
// $display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
// $display("MICRON_SIM = %0d", MICRON_SIM);
// $display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
// $display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
// $display("WB_ERROR = %0d", WB_ERROR);
// $display("BIST_MODE = %0d", BIST_MODE);
// $display("ECC_ENABLE = %0d", ECC_ENABLE);
// $display("DIC = %0d", DIC);
// $display("RTT_NOM = %0d", RTT_NOM);
// $display("SELF_REFRESH = %0d", SELF_REFRESH);
// $display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
// $display("End of DDR3 TOP PARAMETERS\n-----------------------------");
// end
endmodule

12
testbench/ddr3_dimm_micron_sim.sv
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@ -48,23 +48,23 @@ module ddr3_dimm_micron_sim;
`ifdef TWO_LANES_x8
localparam BYTE_LANES = 2,
ODELAY_SUPPORTED = 0;
ODELAY_SUPPORTED = 1;
`endif
`ifdef EIGHT_LANES_x8
localparam BYTE_LANES = 8,
ODELAY_SUPPORTED = 0;
ODELAY_SUPPORTED = 1;
`endif
localparam CONTROLLER_CLK_PERIOD = 5_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 1_250, //ps, period of clock input to DDR3 RAM device
localparam CONTROLLER_CLK_PERIOD = 12_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 3_000, //ps, period of clock input to DDR3 RAM device
AUX_WIDTH = 16, // AUX lines
ECC_ENABLE = 0, // ECC enable
SELF_REFRESH = 2'b00,
DUAL_RANK_DIMM = 0,
TEST_SELF_REFRESH = 0,
SKIP_INTERNAL_TEST = 0;
BIST_MODE = ; // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
@ -168,7 +168,7 @@ ddr3_top #(
.SECOND_WISHBONE(0), //set to 1 if 2nd wishbone for debugging is needed
.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
.WB_ERROR(1), // set to 1 to support Wishbone error (asserts at ECC double bit error)
.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
.BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
.SELF_REFRESH(SELF_REFRESH), // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
.DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 = enable, 0 = disable)
) ddr3_top

4
testbench/sim_defines.vh
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@ -1,6 +1,6 @@
// Define either TWO_LANES_x8 or EIGHT_LANES_x8
`define TWO_LANES_x8
//`define EIGHT_LANES_x8
//`define TWO_LANES_x8
`define EIGHT_LANES_x8
`ifdef EIGHT_LANES_x8
`ifdef TWO_LANES_x8

44
testbench/xsim/regression_test.sh
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@ -2,28 +2,28 @@
#################################################################################################################
# Define the test configurations (CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD, ODELAY_SUPPORTED, LANES_OPTION, ADD_BUS_DELAY)
# Define the test configurations (CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD, ODELAY_SUPPORTED, LANES_OPTION, ADD_BUS_DELAY, BIST_MODE)
TESTS=(
# with bus delay
"12_000 3_000 1 EIGHT_LANES 1" # DDR3-666
"10_000 2_500 1 EIGHT_LANES 1" # DDR3-800
"6_000 1_500 1 EIGHT_LANES 1" # DDR3-1333 write dm is weird (two happens at same time???)
"5_000 1_250 1 EIGHT_LANES 1" # DDR3-1600
"12_000 3_000 1 EIGHT_LANES 1 1" # DDR3-666
"10_000 2_500 1 EIGHT_LANES 1 1" # DDR3-800
"6_000 1_500 1 EIGHT_LANES 1 2" # DDR3-1333 write dm is weird (two happens at same time???)
"5_000 1_250 1 EIGHT_LANES 1 2" # DDR3-1600
# No bus delays
"12_000 3_000 1 EIGHT_LANES 0"
"10_000 2_500 1 EIGHT_LANES 0"
"6_000 1_500 1 EIGHT_LANES 0"
"5_000 1_250 1 EIGHT_LANES 0"
"12_000 3_000 1 EIGHT_LANES 0 2"
"10_000 2_500 1 EIGHT_LANES 0 2"
"6_000 1_500 1 EIGHT_LANES 0 1"
"5_000 1_250 1 EIGHT_LANES 0 1"
# x16
"12_000 3_000 1 TWO_LANES 0"
"10_000 2_500 1 TWO_LANES 0"
"6_000 1_500 1 TWO_LANES 0"
"5_000 1_250 1 TWO_LANES 0"
"12_000 3_000 1 TWO_LANES 1 1"
"10_000 2_500 1 TWO_LANES 1 1"
"6_000 1_500 1 TWO_LANES 1 2"
"5_000 1_250 1 TWO_LANES 1 2"
# no odelay
"12_000 3_000 0 TWO_LANES 0"
"10_000 2_500 0 TWO_LANES 0"
"6_000 1_500 0 TWO_LANES 0"
"5_000 1_250 0 TWO_LANES 0"
"12_000 3_000 0 TWO_LANES 0 2"
"10_000 2_500 0 TWO_LANES 0 2"
"6_000 1_500 0 TWO_LANES 0 1"
"5_000 1_250 0 TWO_LANES 0 1"
)
#################################################################################################################
@ -57,14 +57,14 @@ fi
index=1
for TEST in "${TESTS[@]}"; do
# Parse the test configuration into individual variables
read -r CONTROLLER_CLK_PERIOD DDR3_CLK_PERIOD ODELAY_SUPPORTED LANES_OPTION ADD_BUS_DELAY <<< "$TEST"
read -r CONTROLLER_CLK_PERIOD DDR3_CLK_PERIOD ODELAY_SUPPORTED LANES_OPTION ADD_BUS_DELAY BIST_MODE <<< "$TEST"
# Record the start time
start_time=$(date +%s)
start_time_am_pm=$(date +"%I:%M %p") # Time in AM-PM format
# Print the current test configuration with the start time
echo "$index. Running test with CONTROLLER_CLK_PERIOD=$CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD=$DDR3_CLK_PERIOD, ODELAY_SUPPORTED=$ODELAY_SUPPORTED, LANES_OPTION=$LANES_OPTION, ADD_BUS_DELAY=$ADD_BUS_DELAY"
echo "$index. Running test with CONTROLLER_CLK_PERIOD=$CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD=$DDR3_CLK_PERIOD, ODELAY_SUPPORTED=$ODELAY_SUPPORTED, LANES_OPTION=$LANES_OPTION, ADD_BUS_DELAY=$ADD_BUS_DELAY, BIST_MODE=$BIST_MODE"
echo " Test started at: $start_time_am_pm"
# Use sed to perform the replacements in the main file
@ -72,6 +72,7 @@ for TEST in "${TESTS[@]}"; do
-e "s/CONTROLLER_CLK_PERIOD = [0-9_]\+/CONTROLLER_CLK_PERIOD = $CONTROLLER_CLK_PERIOD/" \
-e "s/DDR3_CLK_PERIOD = [0-9_]\+/DDR3_CLK_PERIOD = $DDR3_CLK_PERIOD/" \
-e "s/ODELAY_SUPPORTED = [01]/ODELAY_SUPPORTED = $ODELAY_SUPPORTED/" \
-e "s/BIST_MODE = [0-2]/BIST_MODE = $BIST_MODE/" \
"$FILENAME"
# Modify the sim_defines.vh file based on LANES_OPTION
@ -118,9 +119,10 @@ for TEST in "${TESTS[@]}"; do
fi
# Run the simulation script with the respective log file
LOG_FILE="./test_${CONTROLLER_CLK_PERIOD}_ddr3_${DDR3_CLK_PERIOD}_odelay_${ODELAY_SUPPORTED}_lanes_${LANES_OPTION,,}_bus_delay_${ADD_BUS_DELAY}.log"
LOG_FILE="./test_${CONTROLLER_CLK_PERIOD}_ddr3_${DDR3_CLK_PERIOD}_odelay_${ODELAY_SUPPORTED}_lanes_${LANES_OPTION,,}_bus_delay_${ADD_BUS_DELAY}_bist_${BIST_MODE}.log"
# ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE"
timeout 1h ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE" 2>&1
# add timeout if simulation takes too long
timeout 3h ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE" 2>&1
EXIT_CODE=$? # Capture exit code immediately
if [ $EXIT_CODE -eq 124 ]; then
echo " Error: Simulation timed out after 1 hour!" | tee -a "$LOG_FILE"

24437
testbench/xsim/test_5_000_ddr3_1_250_odelay_0_lanes_two_lanes_bus_delay_0.log
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23959
testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_0.log
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24877
testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_eight_lanes_bus_delay_1.log
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25057
testbench/xsim/test_5_000_ddr3_1_250_odelay_1_lanes_two_lanes_bus_delay_0.log
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