added regression test shell scrip to simulate multiple corners
This commit is contained in:
AngeloJacobo
parent
c81f9044d8
commit
016df010c7
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@ -2,3 +2,11 @@ formal/ddr3_multiconfig*prf*
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formal/ecc/
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formal/ddr3_singleconfig/
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example_demo/nexys_video/build/
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testbench/xsim/xsim*
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testbench/xsim/*backup*
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testbench/xsim/*.log
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testbench/xsim/*.pb
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testbench/xsim/*.wdb
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# But do not ignore testbench/xsim/test_*.log
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!testbench/xsim/test_*.log
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@ -425,15 +425,15 @@
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parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
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parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
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parameter DEBUG = 0; // Turn on Debug messages
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parameter BUS_DELAY = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_0 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_1 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_2 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_3 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_4 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_5 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_6 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_7 = 0; // delay in picoseconds
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parameter BUS_DELAY = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_0 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_1 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_2 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_3 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_4 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_5 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_6 = 0; // delay in picoseconds
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parameter FLY_BY_DELAY_LANE_7 = 0; // delay in picoseconds
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parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
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parameter RANDOM_SEED = 31913; //seed value for random generator.
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@ -0,0 +1,83 @@
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################################################################################
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# Vivado (TM) v2022.1 (64-bit)
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#
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# README.txt: Please read the sections below to understand the steps required
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# to simulate the design for a simulator, the directory structure
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# and the generated exported files.
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#
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################################################################################
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1. Simulate Design
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To simulate design, cd to the simulator directory and execute the script.
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For example:-
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% cd questa
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% ./top.sh
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The export simulation flow requires the Xilinx pre-compiled simulation library
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components for the target simulator. These components are referred using the
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'-lib_map_path' switch. If this switch is specified, then the export simulation
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will automatically set this library path in the generated script and update,
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copy the simulator setup file(s) in the exported directory.
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If '-lib_map_path' is not specified, then the pre-compiled simulation library
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information will not be included in the exported scripts and that may cause
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simulation errors when running this script. Alternatively, you can provide the
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library information using this switch while executing the generated script.
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For example:-
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% ./top.sh -lib_map_path /design/questa/clibs
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Please refer to the generated script header 'Prerequisite' section for more details.
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2. Directory Structure
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By default, if the -directory switch is not specified, export_simulation will
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create the following directory structure:-
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<current_working_directory>/export_sim/<simulator>
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For example, if the current working directory is /tmp/test, export_simulation
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will create the following directory path:-
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/tmp/test/export_sim/questa
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If -directory switch is specified, export_simulation will create a simulator
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sub-directory under the specified directory path.
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For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
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command will create the following directory:-
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/tmp/test/my_test_area/func_sim/questa
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By default, if -simulator is not specified, export_simulation will create a
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simulator sub-directory for each simulator and export the files for each simulator
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in this sub-directory respectively.
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IMPORTANT: Please note that the simulation library path must be specified manually
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in the generated script for the respective simulator. Please refer to the generated
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script header 'Prerequisite' section for more details.
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3. Exported script and files
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Export simulation will create the driver shell script, setup files and copy the
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design sources in the output directory path.
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By default, when the -script_name switch is not specified, export_simulation will
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create the following script name:-
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<simulation_top>.sh (Unix)
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When exporting the files for an IP using the -of_objects switch, export_simulation
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will create the following script name:-
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<ip-name>.sh (Unix)
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Export simulation will create the setup files for the target simulator specified
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with the -simulator switch.
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For example, if the target simulator is "xcelium", export_simulation will create the
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'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
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file.
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@ -57,13 +57,14 @@ module ddr3_dimm_micron_sim;
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`endif
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localparam CONTROLLER_CLK_PERIOD = 5_000, //7_504, //ps, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 1250, //1_876,//ps, period of clock input to DDR3 RAM device
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localparam CONTROLLER_CLK_PERIOD = 5_000, //ps, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 1_250, //ps, period of clock input to DDR3 RAM device
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AUX_WIDTH = 16, // AUX lines
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ECC_ENABLE = 0, // ECC enable
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SELF_REFRESH = 2'b00,
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DUAL_RANK_DIMM = 0,
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TEST_SELF_REFRESH = 0;
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TEST_SELF_REFRESH = 0,
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SKIP_INTERNAL_TEST = 0;
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reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
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@ -113,7 +114,6 @@ module ddr3_dimm_micron_sim;
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// temperature
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wire user_temp_alarm_out;
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`ifdef USE_CLOCK_WIZARD
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// Use clock wizard
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reg i_clk;
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@ -168,7 +168,7 @@ ddr3_top #(
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.SECOND_WISHBONE(0), //set to 1 if 2nd wishbone for debugging is needed
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.ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC )
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.WB_ERROR(1), // set to 1 to support Wishbone error (asserts at ECC double bit error)
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.SKIP_INTERNAL_TEST(0), // skip built-in self test (would require >2 seconds of internal test right after calibration)
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.SKIP_INTERNAL_TEST(SKIP_INTERNAL_TEST), // skip built-in self test (would require >2 seconds of internal test right after calibration)
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.SELF_REFRESH(SELF_REFRESH), // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
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.DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 = enable, 0 = disable)
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) ddr3_top
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@ -1,6 +1,6 @@
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// Define either TWO_LANES_x8 or EIGHT_LANES_x8
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//`define TWO_LANES_x8
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`define EIGHT_LANES_x8
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`define TWO_LANES_x8
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//`define EIGHT_LANES_x8
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`ifdef EIGHT_LANES_x8
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`ifdef TWO_LANES_x8
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@ -4,7 +4,7 @@
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# README.txt: Please read the sections below to understand the steps required to
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# run the exported script and information about the source files.
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#
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# Generated by export_simulation on Sat Jul 27 15:51:00 PST 2024
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# Generated by export_simulation on Sun Jan 26 11:59:04 PST 2025
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#
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################################################################################
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@ -9,7 +9,7 @@
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# directory, add the library logical mappings in the simulator setup file, create default
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# 'do/prj' file, execute compilation, elaboration and simulation steps.
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#
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# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
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# Generated by Vivado on Sun Jan 26 11:32:37 PST 2025
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# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
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#
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# Tool Version Limit: 2022.04
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@ -46,7 +46,7 @@ compile()
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# RUN_STEP: <elaborate>
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elaborate()
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{
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xelab -generic_top "ECC_ENABLE=1" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
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}
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# RUN_STEP: <simulate>
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@ -64,6 +64,7 @@ setup()
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echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
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exit 1
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fi
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copy_setup_file $2
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;;
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"-reset_run" )
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reset_run
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@ -74,6 +75,7 @@ setup()
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# do not remove previous data
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;;
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* )
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copy_setup_file $2
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esac
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# Add any setup/initialization commands here:-
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@ -82,6 +84,90 @@ setup()
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}
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# Copy xsim.ini file
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copy_setup_file()
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{
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file="xsim.ini"
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lib_map_path="/tools/Xilinx/Vivado/2022.1/data/xsim"
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if [[ ($1 != "") ]]; then
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lib_map_path="$1"
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fi
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if [[ ($lib_map_path != "") ]]; then
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src_file="$lib_map_path/$file"
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if [[ -e $src_file ]]; then
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cp $src_file .
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fi
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# Map local design libraries to xsim.ini
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map_local_libs
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fi
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}
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# Map local design libraries
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map_local_libs()
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{
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updated_mappings=()
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local_mappings=()
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# Local design libraries
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local_libs=()
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if [[ 0 == ${#local_libs[@]} ]]; then
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return
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fi
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file="xsim.ini"
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file_backup="xsim.ini.bak"
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if [[ -e $file ]]; then
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rm -f $file_backup
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# Create a backup copy of the xsim.ini file
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cp $file $file_backup
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# Read libraries from backup file and search in local library collection
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while read -r line
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do
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IN=$line
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# Split mapping entry with '=' delimiter to fetch library name and mapping
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read lib_name mapping <<<$(IFS="="; echo $IN)
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# If local library found, then construct the local mapping and add to local mapping collection
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if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
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line="$lib_name=xsim.dir/$lib_name"
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local_mappings+=("$lib_name")
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fi
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# Add to updated library mapping collection
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updated_mappings+=("$line")
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done < "$file_backup"
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# Append local libraries not found originally from xsim.ini
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for (( i=0; i<${#local_libs[*]}; i++ )); do
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lib_name="${local_libs[i]}"
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if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
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line="$lib_name=xsim.dir/$lib_name"
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updated_mappings+=("$line")
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fi
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done
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# Write updated mappings in xsim.ini
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rm -f $file
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for (( i=0; i<${#updated_mappings[*]}; i++ )); do
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lib_name="${updated_mappings[i]}"
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echo $lib_name >> $file
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done
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else
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for (( i=0; i<${#local_libs[*]}; i++ )); do
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lib_name="${local_libs[i]}"
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mapping="$lib_name=xsim.dir/$lib_name"
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echo $mapping >> $file
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done
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fi
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}
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# Delete generated data from the previous run
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reset_run()
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{
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@ -1,9 +1,7 @@
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ddr3_controller.v,verilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="../"
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ddr3_phy.v,verilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="../"
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ddr3_top.v,verilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ddr3_top.v,incdir="../"
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ddr3.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/testbench/ddr3.sv,incdir="../"
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ddr3.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="../"
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ecc_dec.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ecc/ecc_dec.sv,incdir="../"
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ecc_enc.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/rtl/ecc/ecc_enc.sv,incdir="../"
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ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="../"
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glbl.v,Verilog,xil_defaultlib,glbl.v
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ddr3_controller.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_phy.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_top.v,verilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_module.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv,incdir="/home/ajacobo/Desktop/UberDDR3/testbench"incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"
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glbl.v,Verilog,xil_defaultlib,/home/ajacobo/incdir="/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0"/glbl.v
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@ -0,0 +1,143 @@
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#!/bin/bash
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#################################################################################################################
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# Define the test configurations (CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD, ODELAY_SUPPORTED, LANES_OPTION, ADD_BUS_DELAY)
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TESTS=(
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# with bus delay
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"12_000 3_000 1 EIGHT_LANES 1" # DDR3-666
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"10_000 2_500 1 EIGHT_LANES 1" # DDR3-800
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"6_000 1_500 1 EIGHT_LANES 1" # DDR3-1333 write dm is weird (two happens at same time???)
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"5_000 1_250 1 EIGHT_LANES 1" # DDR3-1600
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# No bus delays
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"12_000 3_000 1 EIGHT_LANES 0"
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"10_000 2_500 1 EIGHT_LANES 0"
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"6_000 1_500 1 EIGHT_LANES 0"
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"5_000 1_250 1 EIGHT_LANES 0"
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# x16
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"12_000 3_000 1 TWO_LANES 0"
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"10_000 2_500 1 TWO_LANES 0"
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"6_000 1_500 1 TWO_LANES 0"
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"5_000 1_250 1 TWO_LANES 0"
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# no odelay
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"12_000 3_000 0 TWO_LANES 0"
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"10_000 2_500 0 TWO_LANES 0"
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"6_000 1_500 0 TWO_LANES 0"
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"5_000 1_250 0 TWO_LANES 0"
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)
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#################################################################################################################
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# Define the files to modify
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FILENAME="../ddr3_dimm_micron_sim.sv"
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DEFINES_FILE="../sim_defines.vh"
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PARAMETERS_FILE="../8192Mb_ddr3_parameters.vh"
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# Check if the main file exists
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if [[ ! -f "$FILENAME" ]]; then
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echo "Error: File '$FILENAME' does not exist."
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exit 1
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fi
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# Check if the defines file exists
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if [[ ! -f "$DEFINES_FILE" ]]; then
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echo "Error: File '$DEFINES_FILE' does not exist."
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exit 1
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fi
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# Check if the parameters file exists
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if [[ ! -f "$PARAMETERS_FILE" ]]; then
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echo "Error: File '$PARAMETERS_FILE' does not exist."
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exit 1
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fi
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#################################################################################################################
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# Loop over each test configuration
|
||||
index=1
|
||||
for TEST in "${TESTS[@]}"; do
|
||||
# Parse the test configuration into individual variables
|
||||
read -r CONTROLLER_CLK_PERIOD DDR3_CLK_PERIOD ODELAY_SUPPORTED LANES_OPTION ADD_BUS_DELAY <<< "$TEST"
|
||||
|
||||
# Record the start time
|
||||
start_time=$(date +%s)
|
||||
start_time_am_pm=$(date +"%I:%M %p") # Time in AM-PM format
|
||||
|
||||
# Print the current test configuration with the start time
|
||||
echo "$index. Running test with CONTROLLER_CLK_PERIOD=$CONTROLLER_CLK_PERIOD, DDR3_CLK_PERIOD=$DDR3_CLK_PERIOD, ODELAY_SUPPORTED=$ODELAY_SUPPORTED, LANES_OPTION=$LANES_OPTION, ADD_BUS_DELAY=$ADD_BUS_DELAY"
|
||||
echo " Test started at: $start_time_am_pm"
|
||||
|
||||
# Use sed to perform the replacements in the main file
|
||||
sed -i \
|
||||
-e "s/CONTROLLER_CLK_PERIOD = [0-9_]\+/CONTROLLER_CLK_PERIOD = $CONTROLLER_CLK_PERIOD/" \
|
||||
-e "s/DDR3_CLK_PERIOD = [0-9_]\+/DDR3_CLK_PERIOD = $DDR3_CLK_PERIOD/" \
|
||||
-e "s/ODELAY_SUPPORTED = [01]/ODELAY_SUPPORTED = $ODELAY_SUPPORTED/" \
|
||||
"$FILENAME"
|
||||
|
||||
# Modify the sim_defines.vh file based on LANES_OPTION
|
||||
if [[ "$LANES_OPTION" == "TWO_LANES" ]]; then
|
||||
sed -i \
|
||||
-e "s|^//\(\`define TWO_LANES_x8\)|\1|" \
|
||||
-e "s|^\(\`define EIGHT_LANES_x8\)|//\1|" \
|
||||
"$DEFINES_FILE"
|
||||
elif [[ "$LANES_OPTION" == "EIGHT_LANES" ]]; then
|
||||
sed -i \
|
||||
-e "s|^//\(\`define EIGHT_LANES_x8\)|\1|" \
|
||||
-e "s|^\(\`define TWO_LANES_x8\)|//\1|" \
|
||||
"$DEFINES_FILE"
|
||||
else
|
||||
echo "Error: Invalid LANES_OPTION value. Choose either 'TWO_LANES' or 'EIGHT_LANES'."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
# Modify the parameters file based on ADD_BUS_DELAY
|
||||
if [[ "$ADD_BUS_DELAY" == "1" ]]; then
|
||||
sed -i \
|
||||
-e "s|BUS_DELAY = [0-9]\+|BUS_DELAY = 100|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_0 = [0-9]\+|FLY_BY_DELAY_LANE_0 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_1 = [0-9]\+|FLY_BY_DELAY_LANE_1 = 50|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_2 = [0-9]\+|FLY_BY_DELAY_LANE_2 = 100|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_3 = [0-9]\+|FLY_BY_DELAY_LANE_3 = 150|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_4 = [0-9]\+|FLY_BY_DELAY_LANE_4 = 200|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_5 = [0-9]\+|FLY_BY_DELAY_LANE_5 = 250|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_6 = [0-9]\+|FLY_BY_DELAY_LANE_6 = 300|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_7 = [0-9]\+|FLY_BY_DELAY_LANE_7 = 350|" \
|
||||
"$PARAMETERS_FILE"
|
||||
else
|
||||
sed -i \
|
||||
-e "s|BUS_DELAY = [0-9]\+|BUS_DELAY = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_0 = [0-9]\+|FLY_BY_DELAY_LANE_0 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_1 = [0-9]\+|FLY_BY_DELAY_LANE_1 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_2 = [0-9]\+|FLY_BY_DELAY_LANE_2 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_3 = [0-9]\+|FLY_BY_DELAY_LANE_3 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_4 = [0-9]\+|FLY_BY_DELAY_LANE_4 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_5 = [0-9]\+|FLY_BY_DELAY_LANE_5 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_6 = [0-9]\+|FLY_BY_DELAY_LANE_6 = 0|" \
|
||||
-e "s|FLY_BY_DELAY_LANE_7 = [0-9]\+|FLY_BY_DELAY_LANE_7 = 0|" \
|
||||
"$PARAMETERS_FILE"
|
||||
fi
|
||||
|
||||
# Run the simulation script with the respective log file
|
||||
LOG_FILE="./test_${CONTROLLER_CLK_PERIOD}_ddr3_${DDR3_CLK_PERIOD}_odelay_${ODELAY_SUPPORTED}_lanes_${LANES_OPTION,,}_bus_delay_${ADD_BUS_DELAY}.log"
|
||||
# ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE"
|
||||
timeout 1h ./ddr3_dimm_micron_sim.sh >> "$LOG_FILE" 2>&1
|
||||
EXIT_CODE=$? # Capture exit code immediately
|
||||
if [ $EXIT_CODE -eq 124 ]; then
|
||||
echo " Error: Simulation timed out after 1 hour!" | tee -a "$LOG_FILE"
|
||||
fi
|
||||
|
||||
# Record the end time and calculate the duration in minutes
|
||||
end_time=$(date +%s)
|
||||
duration=$((end_time - start_time))
|
||||
minutes=$((duration / 60))
|
||||
seconds=$((duration % 60))
|
||||
|
||||
# Report the results
|
||||
echo " Test completed. Duration: ${minutes}m ${seconds}s. Results saved to '$LOG_FILE'."
|
||||
echo ""
|
||||
|
||||
# Increment the index
|
||||
((index++))
|
||||
done
|
||||
|
||||
#################################################################################################################
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
rm -rf *backup*
|
||||
rm -rf *test_ecc*.log*
|
||||
echo -e "\e[32mRun test: test_ecc_0 \e[0m"
|
||||
./test_ecc_0.sh -reset_run
|
||||
./test_ecc_0.sh >> ./test_ecc_0.log
|
||||
./test_ecc_0.sh -reset_run
|
||||
|
||||
echo ""
|
||||
echo ""
|
||||
echo -e "\e[32mRun test: test_ecc_1 \e[0m"
|
||||
./test_ecc_1.sh >> ./test_ecc_1.log
|
||||
./test_ecc_1.sh -reset_run
|
||||
|
||||
echo ""
|
||||
echo ""
|
||||
echo -e "\e[32mRun test: test_ecc_2 \e[0m"
|
||||
./test_ecc_2.sh >> ./test_ecc_2.log
|
||||
./test_ecc_2.sh -reset_run
|
||||
|
||||
echo ""
|
||||
echo ""
|
||||
echo -e "\e[32mRun test: test_ecc_3 \e[0m"
|
||||
./test_ecc_3.sh >> ./test_ecc_3.log
|
||||
./test_ecc_3.sh -reset_run
|
||||
|
||||
rm -rf *backup*
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,129 +0,0 @@
|
|||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2022.1 (64-bit)
|
||||
#
|
||||
# Filename : ddr3_dimm_micron_sim.sh
|
||||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
|
||||
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.04
|
||||
#
|
||||
# usage: ddr3_dimm_micron_sim.sh [-help]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-reset_run]
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Set xvlog options
|
||||
xvlog_opts="--incr --relax -L uvm"
|
||||
|
||||
# Script info
|
||||
echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2022.1 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
xelab -generic_top "ECC_ENABLE=0" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,129 +0,0 @@
|
|||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2022.1 (64-bit)
|
||||
#
|
||||
# Filename : ddr3_dimm_micron_sim.sh
|
||||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
|
||||
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.04
|
||||
#
|
||||
# usage: ddr3_dimm_micron_sim.sh [-help]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-reset_run]
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Set xvlog options
|
||||
xvlog_opts="--incr --relax -L uvm"
|
||||
|
||||
# Script info
|
||||
echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2022.1 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
xelab -generic_top "ECC_ENABLE=2" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,129 +0,0 @@
|
|||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2022.1 (64-bit)
|
||||
#
|
||||
# Filename : ddr3_dimm_micron_sim.sh
|
||||
# Simulator : Xilinx Vivado Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sat Jul 27 15:51:00 PST 2024
|
||||
# SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
|
||||
#
|
||||
# Tool Version Limit: 2022.04
|
||||
#
|
||||
# usage: ddr3_dimm_micron_sim.sh [-help]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-lib_map_path]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-noclean_files]
|
||||
# usage: ddr3_dimm_micron_sim.sh [-reset_run]
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Set xvlog options
|
||||
xvlog_opts="--incr --relax -L uvm"
|
||||
|
||||
# Script info
|
||||
echo -e "ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2022.1 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
xelab -generic_top "ECC_ENABLE=3" --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
xsim ddr3_dimm_micron_sim -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -tclbatch cmd.tcl -log simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ddr3_dimm_micron_sim.wdb xsim.dir)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ddr3_dimm_micron_sim.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ddr3_dimm_micron_sim.sh [-help]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-lib_map_path]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-reset_run]\n\
|
||||
Usage: ddr3_dimm_micron_sim.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
|
|
@ -1,15 +1,13 @@
|
|||
verilog xil_defaultlib --include "../" \
|
||||
"../../rtl/ddr3_controller.v" \
|
||||
"../../rtl/ddr3_phy.v" \
|
||||
"../../rtl/ddr3_top.v" \
|
||||
verilog xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \
|
||||
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_controller.v" \
|
||||
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_phy.v" \
|
||||
"/home/ajacobo/Desktop/UberDDR3/rtl/ddr3_top.v" \
|
||||
|
||||
sv xil_defaultlib --include "../" \
|
||||
"../ddr3.sv" \
|
||||
"../../rtl/ecc/ecc_dec.sv" \
|
||||
"../../rtl/ecc/ecc_enc.sv" \
|
||||
"../ddr3_dimm_micron_sim.sv" \
|
||||
"../ddr3_module.sv" \
|
||||
sv xil_defaultlib --include "/home/ajacobo/Desktop/UberDDR3/testbench" --include "/home/ajacobo/Desktop/enclustra_vivado/enclustra_vivado.gen/sources_1/ip/clk_wiz_0" \
|
||||
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3.sv" \
|
||||
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_module.sv" \
|
||||
"/home/ajacobo/Desktop/UberDDR3/testbench/ddr3_dimm_micron_sim.sv" \
|
||||
|
||||
verilog xil_defaultlib "glbl.v"
|
||||
verilog xil_defaultlib "/home/ajacobo/Desktop/UberDDR3/testbench/xsim/glbl.v"
|
||||
|
||||
nosort
|
||||
|
|
|
|||
|
|
@ -1 +1,480 @@
|
|||
xil_defaultlib=xsim.dir/xil_defaultlib
|
||||
std=$RDI_DATADIR/xsim/vhdl/std
|
||||
ieee=$RDI_DATADIR/xsim/vhdl/ieee
|
||||
ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
|
||||
vl=$RDI_DATADIR/xsim/vhdl/vl
|
||||
synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
|
||||
uvm=$RDI_DATADIR/xsim/system_verilog/uvm
|
||||
secureip=$RDI_DATADIR/xsim/verilog/secureip
|
||||
unisim=$RDI_DATADIR/xsim/vhdl/unisim
|
||||
unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
|
||||
unifast=$RDI_DATADIR/xsim/vhdl/unifast
|
||||
unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
|
||||
unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
|
||||
unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
|
||||
simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
|
||||
gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
|
||||
microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
|
||||
emb_mem_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_6
|
||||
common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
|
||||
ptp_1588_timer_syncer_v2_0_3=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_3
|
||||
tcc_decoder_3gppmm_v2_0_23=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_23
|
||||
v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2
|
||||
fc32_rs_fec_v1_0_21=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_21
|
||||
vid_phy_controller_v2_1_13=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_13
|
||||
aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1
|
||||
axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
|
||||
axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
|
||||
noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
|
||||
axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
|
||||
v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9
|
||||
axi_firewall_v1_2_1=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_1
|
||||
xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
|
||||
axi_mm2s_mapper_v1_1_25=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_25
|
||||
v_tpg_v8_1_5=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_5
|
||||
ll_compress_v1_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_1_0
|
||||
cpm4_v1_0_7=$RDI_DATADIR/xsim/ip/cpm4_v1_0_7
|
||||
axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
|
||||
convolution_v9_0_16=$RDI_DATADIR/xsim/ip/convolution_v9_0_16
|
||||
tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
|
||||
axi_timebase_wdt_v3_0_18=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_18
|
||||
xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
|
||||
axi_epc_v2_0_29=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_29
|
||||
dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
|
||||
axi_interconnect_v1_7_20=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_20
|
||||
gmii_to_rgmii_v4_1_4=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_4
|
||||
clk_gen_sim_v1_0_2=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_2
|
||||
ieee802d3_50g_rs_fec_v2_0_11=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_11
|
||||
axi_datamover_v5_1_28=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_28
|
||||
zynq_ultra_ps_e_vip_v1_0_12=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_12
|
||||
xscl=$RDI_DATADIR/xsim/ip/xscl
|
||||
bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
|
||||
vby1hs_v1_0_2=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_2
|
||||
tmr_manager_v1_0_9=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_9
|
||||
polar_v1_1_0=$RDI_DATADIR/xsim/ip/polar_v1_1_0
|
||||
vitis_net_p4_v1_1_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_1_0
|
||||
timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
|
||||
mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
|
||||
fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
|
||||
vid_phy_controller_v2_2_13=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_13
|
||||
noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
|
||||
xpm_cdc_gen_v1_0_1=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_1
|
||||
ethernet_1_10_25g_v2_7_5=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_5
|
||||
axi_register_slice_v2_1_26=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_26
|
||||
hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
|
||||
v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1
|
||||
axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24
|
||||
axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
|
||||
zynq_ultra_ps_e_v3_3_7=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_7
|
||||
axi_sg_v4_1_15=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_15
|
||||
xdma_v4_1_17=$RDI_DATADIR/xsim/ip/xdma_v4_1_17
|
||||
axi_uartlite_v2_0_30=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_30
|
||||
bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
|
||||
shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
|
||||
noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
|
||||
axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
|
||||
axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
|
||||
uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2
|
||||
amm_axi_bridge_v1_0_12=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_12
|
||||
rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
|
||||
pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
|
||||
displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
|
||||
remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
|
||||
fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
|
||||
noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
|
||||
ieee802d3_50g_rs_fec_v1_0_19=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_19
|
||||
pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
|
||||
axis_dwidth_converter_v1_1_25=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_25
|
||||
ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
|
||||
v_vcresampler_v1_1_5=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_5
|
||||
xdfe_resampler_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_4
|
||||
v_axi4s_remap_v1_0_19=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_19
|
||||
xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
|
||||
axi_timer_v2_0_28=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_28
|
||||
xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
|
||||
xdfe_equalizer_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_4
|
||||
gtwizard_ultrascale_v1_6_13=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_13
|
||||
axis_clock_converter_v1_1_27=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_27
|
||||
tsn_endpoint_ethernet_mac_block_v1_0_11=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_11
|
||||
axis_vio_v1_0_6=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_6
|
||||
dfx_controller_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_3
|
||||
axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
|
||||
ahblite_axi_bridge_v3_0_21=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_21
|
||||
v_smpte_uhdsdi_tx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_1
|
||||
viterbi_v9_1_13=$RDI_DATADIR/xsim/ip/viterbi_v9_1_13
|
||||
axi4stream_vip_v1_1_12=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_12
|
||||
etrnic_v1_1_5=$RDI_DATADIR/xsim/ip/etrnic_v1_1_5
|
||||
adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
|
||||
ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
|
||||
axi_data_fifo_v2_1_25=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_25
|
||||
axi_dwidth_converter_v2_1_26=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_26
|
||||
cordic_v6_0_18=$RDI_DATADIR/xsim/ip/cordic_v6_0_18
|
||||
axi_lmb_bridge_v1_0_0=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_0
|
||||
g975_efec_i7_v2_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_18
|
||||
c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14
|
||||
trace_s2mm_v1_2_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v1_2_0
|
||||
axis_broadcaster_v1_1_25=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_25
|
||||
axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
|
||||
v_tc_v6_2_4=$RDI_DATADIR/xsim/ip/v_tc_v6_2_4
|
||||
icap_arb_v1_0_1=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_1
|
||||
dsp_macro_v1_0_2=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_2
|
||||
v_dp_axi4s_vid_out_v1_0_4=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_4
|
||||
v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
|
||||
qdriv_pl_v1_0_7=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_7
|
||||
proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
|
||||
v_axi4s_remap_v1_1_5=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_5
|
||||
pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10
|
||||
fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
|
||||
mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
|
||||
axi_hwicap_v3_0_30=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_30
|
||||
hdmi_gt_controller_v1_0_7=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_7
|
||||
axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
|
||||
iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
|
||||
axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
|
||||
ta_dma_v1_0_10=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_10
|
||||
xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0
|
||||
canfd_v3_0_5=$RDI_DATADIR/xsim/ip/canfd_v3_0_5
|
||||
dcmac_v2_0_0=$RDI_DATADIR/xsim/ip/dcmac_v2_0_0
|
||||
axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
|
||||
axi_msg_v1_0_8=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_8
|
||||
axi_vdma_v6_3_14=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_14
|
||||
v_vid_in_axi4s_v5_0_1=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_1
|
||||
debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
|
||||
lmb_bram_if_cntlr_v4_0_21=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_21
|
||||
axi_tg_lib=$RDI_DATADIR/xsim/ip/axi_tg_lib
|
||||
v_scenechange_v1_1_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_4
|
||||
in_system_ibert_v1_0_16=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_16
|
||||
tmr_sem_v1_0_22=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_22
|
||||
pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
|
||||
axi_iic_v2_1_2=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_2
|
||||
xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
|
||||
axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
|
||||
g709_fec_v2_4_5=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_5
|
||||
high_speed_selectio_wiz_v3_6_3=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_3
|
||||
xtlm=$RDI_DATADIR/xsim/ip/xtlm
|
||||
v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
|
||||
xdfe_fft_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_4
|
||||
axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
|
||||
v_warp_filter_v1_1_0=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_0
|
||||
c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
|
||||
axi_fifo_mm_s_v4_2_8=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_8
|
||||
util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
|
||||
usxgmii_v1_2_7=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_7
|
||||
blk_mem_gen_v8_4_5=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_5
|
||||
ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7
|
||||
axi_traffic_gen_v3_0_12=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_12
|
||||
dfx_decoupler_v1_0_4=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_4
|
||||
util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
|
||||
emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
|
||||
lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
|
||||
rama_v1_1_12_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_12_lib
|
||||
hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
|
||||
xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
|
||||
xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
|
||||
ieee802d3_400g_rs_fec_v2_0_7=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_7
|
||||
lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
|
||||
v_hdmi_phy1_v1_0_6=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_6
|
||||
axis_data_fifo_v2_0_8=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_8
|
||||
ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
|
||||
picxo=$RDI_DATADIR/xsim/ip/picxo
|
||||
axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
|
||||
xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
|
||||
v_hdmi_tx1_v1_0_3=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_3
|
||||
axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
|
||||
axi_sideband_util_v1_0_10=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_10
|
||||
v_demosaic_v1_1_5=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_5
|
||||
lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
|
||||
cmac_v2_6_7=$RDI_DATADIR/xsim/ip/cmac_v2_6_7
|
||||
fifo_generator_v13_2_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_7
|
||||
pc_cfr_v7_0_1=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_1
|
||||
gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
|
||||
video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4
|
||||
axi_usb2_device_v5_0_27=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_27
|
||||
shell_utils_addr_remap_v1_0_5=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_5
|
||||
xbip_multadd_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_17
|
||||
axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
|
||||
axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
|
||||
axi_mcdma_v1_1_7=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_7
|
||||
xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
|
||||
pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2
|
||||
lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
|
||||
i2s_transmitter_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_5
|
||||
xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
|
||||
xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
|
||||
noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
|
||||
c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
|
||||
processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
|
||||
rld3_pl_v1_0_9=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_9
|
||||
versal_cips_ps_vip_v1_0_4=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_4
|
||||
multi_channel_25g_rs_fec_v1_0_18=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_18
|
||||
v_letterbox_v1_1_5=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_5
|
||||
axis_interconnect_v1_1_20=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_20
|
||||
axi_uart16550_v2_0_28=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_28
|
||||
roe_framer_v3_0_3=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_3
|
||||
ddr4_pl_v1_0_8=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_8
|
||||
sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
|
||||
i2s_receiver_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_5
|
||||
axi_crossbar_v2_1_27=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_27
|
||||
axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
|
||||
compact_gt_v1_0_12=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_12
|
||||
v_mix_v5_2_3=$RDI_DATADIR/xsim/ip/v_mix_v5_2_3
|
||||
div_gen_v5_1_19=$RDI_DATADIR/xsim/ip/div_gen_v5_1_19
|
||||
interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
|
||||
zynq_ultra_ps_e_v3_4_0=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_4_0
|
||||
hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
|
||||
pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
|
||||
mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
|
||||
axi_mmu_v2_1_24=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_24
|
||||
can_v5_0_29=$RDI_DATADIR/xsim/ip/can_v5_0_29
|
||||
v_tpg_v8_2_1=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_1
|
||||
sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
|
||||
sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
|
||||
v_csc_v1_1_5=$RDI_DATADIR/xsim/ip/v_csc_v1_1_5
|
||||
v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
|
||||
v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2
|
||||
axis_register_slice_v1_1_26=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_26
|
||||
c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14
|
||||
trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
|
||||
axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
|
||||
fast_adapter_v1_0_3=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_3
|
||||
system_cache_v5_0_8=$RDI_DATADIR/xsim/ip/system_cache_v5_0_8
|
||||
v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
|
||||
ieee802d3_rs_fec_v2_0_15=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_15
|
||||
v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
|
||||
perf_axi_tg_v1_0_8=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_8
|
||||
sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
|
||||
mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
|
||||
ilknf_v1_1_0=$RDI_DATADIR/xsim/ip/ilknf_v1_1_0
|
||||
rs_decoder_v9_0_18=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_18
|
||||
axi_chip2chip_v5_0_15=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_15
|
||||
qdma_v4_0_11=$RDI_DATADIR/xsim/ip/qdma_v4_0_11
|
||||
ldpc_v2_0_10=$RDI_DATADIR/xsim/ip/ldpc_v2_0_10
|
||||
axi_c2c_v1_0_3=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_3
|
||||
av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
|
||||
pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
|
||||
xxv_ethernet_v4_1_0=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_0
|
||||
vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
|
||||
rs_toolbox_v9_0_9=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_9
|
||||
axis_data_fifo_v1_1_27=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_27
|
||||
audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
|
||||
c_counter_binary_v12_0_15=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_15
|
||||
axi_dma_v7_1_27=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_27
|
||||
emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
|
||||
axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
|
||||
dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
|
||||
axi_gpio_v2_0_28=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_28
|
||||
v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
|
||||
axi_emc_v3_0_26=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_26
|
||||
dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
|
||||
axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
|
||||
microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
|
||||
mdm_v3_2_23=$RDI_DATADIR/xsim/ip/mdm_v3_2_23
|
||||
mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
|
||||
noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0
|
||||
v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
|
||||
axi_vfifo_ctrl_v2_0_28=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_28
|
||||
stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
|
||||
axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
|
||||
cic_compiler_v4_0_16=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_16
|
||||
mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15
|
||||
stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
|
||||
ieee802d3_200g_rs_fec_v2_0_5=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_5
|
||||
xdfe_cc_filter_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_0_4
|
||||
advanced_io_wizard_v1_0_7=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_7
|
||||
nvmeha_v1_0_7=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_7
|
||||
axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
|
||||
smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
|
||||
mrmac_v1_6_0=$RDI_DATADIR/xsim/ip/mrmac_v1_6_0
|
||||
jesd204c_v4_2_8=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_8
|
||||
axi_firewall_v1_1_5=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_5
|
||||
an_lt_v1_0_6=$RDI_DATADIR/xsim/ip/an_lt_v1_0_6
|
||||
lmb_v10_v3_0_12=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_12
|
||||
ats_switch_v1_0_5=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_5
|
||||
switch_core_top_v1_0_11=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_11
|
||||
axi_tft_v2_0_25=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_25
|
||||
xdfe_cc_mixer_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v1_0_4
|
||||
hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
|
||||
floating_point_v7_0_20=$RDI_DATADIR/xsim/ip/floating_point_v7_0_20
|
||||
microblaze_v11_0_9=$RDI_DATADIR/xsim/ip/microblaze_v11_0_9
|
||||
tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
|
||||
v_hcresampler_v1_1_5=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_5
|
||||
interlaken_v2_4_11=$RDI_DATADIR/xsim/ip/interlaken_v2_4_11
|
||||
sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
|
||||
xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
|
||||
fir_compiler_v7_2_18=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_18
|
||||
spdif_v2_0_26=$RDI_DATADIR/xsim/ip/spdif_v2_0_26
|
||||
hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
|
||||
v_vid_gt_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_5
|
||||
noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
|
||||
axi_ahblite_bridge_v3_0_23=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_23
|
||||
v_multi_scaler_v1_2_3=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_3
|
||||
axis_protocol_checker_v2_0_10=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_10
|
||||
mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
|
||||
ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10
|
||||
ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2
|
||||
vitis_deadlock_detector_v1_0_1=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_1
|
||||
lib_fifo_v1_0_16=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_16
|
||||
util_vector_logic_v2_0_2=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_2
|
||||
floating_point_v7_1_14=$RDI_DATADIR/xsim/ip/floating_point_v7_1_14
|
||||
c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
|
||||
dds_compiler_v6_0_22=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_22
|
||||
srio_gen2_v4_1_14=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_14
|
||||
axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
|
||||
vfb_v1_0_20=$RDI_DATADIR/xsim/ip/vfb_v1_0_20
|
||||
v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
|
||||
noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
|
||||
xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
|
||||
advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
|
||||
xpm=$RDI_DATADIR/xsim/ip/xpm
|
||||
hdmi_acr_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_0
|
||||
quadsgmii_v3_5_8=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_8
|
||||
xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
|
||||
axi_vip_v1_1_12=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_12
|
||||
av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0
|
||||
axi_protocol_checker_v2_0_12=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_12
|
||||
sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
|
||||
axi4svideo_bridge_v1_0_14=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_14
|
||||
tsn_temac_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_7
|
||||
dfx_bitstream_monitor_v1_0_1=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_1
|
||||
axi_bram_ctrl_v4_1_6=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_6
|
||||
jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
|
||||
dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1
|
||||
ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
|
||||
ll_compress_v2_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v2_1_0
|
||||
ieee802d3_25g_rs_fec_v1_0_23=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_23
|
||||
hbm2e_pl_v1_0_0=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_0
|
||||
flexo_100g_rs_fec_v1_0_21=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_21
|
||||
cpm5_v1_0_7=$RDI_DATADIR/xsim/ip/cpm5_v1_0_7
|
||||
lte_fft_v2_0_22=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_22
|
||||
v_frmbuf_rd_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_0
|
||||
xfft_v9_1_8=$RDI_DATADIR/xsim/ip/xfft_v9_1_8
|
||||
axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
|
||||
lib_bmg_v1_0_14=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_14
|
||||
axi_quad_spi_v3_2_25=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_25
|
||||
pcie_qdma_mailbox_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_0
|
||||
cpri_v8_11_12=$RDI_DATADIR/xsim/ip/cpri_v8_11_12
|
||||
axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17
|
||||
tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
|
||||
jesd204_v7_2_15=$RDI_DATADIR/xsim/ip/jesd204_v7_2_15
|
||||
v_hscaler_v1_1_5=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_5
|
||||
axis_switch_v1_1_26=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_26
|
||||
accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
|
||||
axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
|
||||
noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
|
||||
tri_mode_ethernet_mac_v9_0_22=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_22
|
||||
generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
|
||||
v_warp_init_v1_1_0=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_0
|
||||
rs_encoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_17
|
||||
v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
|
||||
xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
|
||||
nvme_tc_v3_0_1=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_1
|
||||
v_frmbuf_wr_v2_2_5=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_5
|
||||
sd_fec_v1_1_9=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_9
|
||||
cmac_usplus_v3_1_9=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_9
|
||||
ll_compress_v2_0_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_1
|
||||
g709_rs_encoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_8
|
||||
processing_system7_vip_v1_0_14=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_14
|
||||
c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
|
||||
axi_amm_bridge_v1_0_16=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_16
|
||||
lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
|
||||
audio_formatter_v1_0_8=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_8
|
||||
xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
|
||||
bs_switch_v1_0_0=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_0
|
||||
audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
|
||||
videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
|
||||
lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
|
||||
pc_cfr_v7_1_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_1_0
|
||||
v_vscaler_v1_1_5=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_5
|
||||
rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
|
||||
v_frmbuf_rd_v2_3_1=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_1
|
||||
v_axi4s_vid_out_v4_0_14=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_14
|
||||
v_tpg_v8_0_9=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_9
|
||||
v_frmbuf_wr_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_4_0
|
||||
fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
|
||||
fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
|
||||
axi_protocol_converter_v2_1_26=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_26
|
||||
hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
|
||||
axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
|
||||
ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
|
||||
axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
|
||||
mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
|
||||
xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
|
||||
xdfe_nlf_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_0_0
|
||||
soft_ecc_proxy_v1_0_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_1
|
||||
axi_pcie_v2_9_7=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_7
|
||||
c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
|
||||
xdfe_nr_prach_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v1_0_4
|
||||
axi_clock_converter_v2_1_25=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_25
|
||||
gtwizard_ultrascale_v1_7_13=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_13
|
||||
common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
|
||||
displayport_v8_1_5=$RDI_DATADIR/xsim/ip/displayport_v8_1_5
|
||||
blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
|
||||
ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
|
||||
displayport_v9_0_5=$RDI_DATADIR/xsim/ip/displayport_v9_0_5
|
||||
sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
|
||||
dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
|
||||
axi_perf_mon_v5_0_28=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_28
|
||||
uhdsdi_gt_v2_0_8=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_8
|
||||
oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
|
||||
sem_ultra_v3_1_23=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_23
|
||||
v_mix_v5_1_5=$RDI_DATADIR/xsim/ip/v_mix_v5_1_5
|
||||
ten_gig_eth_pcs_pma_v6_0_22=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_22
|
||||
xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
|
||||
gig_ethernet_pcs_pma_v16_2_8=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_8
|
||||
ieee802d3_clause74_fec_v1_0_13=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_13
|
||||
noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
|
||||
v_frmbuf_rd_v2_2_5=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_5
|
||||
l_ethernet_v3_3_0=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_0
|
||||
rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
|
||||
xfft_v7_2_13=$RDI_DATADIR/xsim/ip/xfft_v7_2_13
|
||||
axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
|
||||
v_frmbuf_wr_v2_3_1=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_1
|
||||
axi_cdma_v4_1_26=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_26
|
||||
emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2
|
||||
cmpy_v6_0_21=$RDI_DATADIR/xsim/ip/cmpy_v6_0_21
|
||||
cam_v2_3_0=$RDI_DATADIR/xsim/ip/cam_v2_3_0
|
||||
g975_efec_i4_v1_0_18=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_18
|
||||
dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
|
||||
tmr_voter_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_4
|
||||
mpegtsmux_v1_1_4=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_4
|
||||
xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
|
||||
lte_fft_v2_1_6=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_6
|
||||
axi_intc_v4_1_17=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_17
|
||||
ernic_v3_1_2=$RDI_DATADIR/xsim/ip/ernic_v3_1_2
|
||||
c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
|
||||
tcc_encoder_3gpp_v5_0_18=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_18
|
||||
axi_pcie3_v3_0_22=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_22
|
||||
g709_rs_decoder_v2_2_10=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_10
|
||||
axis_combiner_v1_1_24=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_24
|
||||
clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
|
||||
aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
|
||||
sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
|
||||
v_uhdsdi_audio_v2_0_6=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_6
|
||||
remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
|
||||
polar_v1_0_10=$RDI_DATADIR/xsim/ip/polar_v1_0_10
|
||||
v_hdmi_rx1_v1_0_3=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_3
|
||||
v_gamma_lut_v1_1_5=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_5
|
||||
sid_v8_0_17=$RDI_DATADIR/xsim/ip/sid_v8_0_17
|
||||
axis_subset_converter_v1_1_26=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_26
|
||||
axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
|
||||
oran_radio_if_v2_2_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v2_2_0
|
||||
xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
|
||||
xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
|
||||
axi_hbicap_v1_0_4=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_4
|
||||
sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3
|
||||
sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
|
||||
versal_cips_v3_2_0=$RDI_DATADIR/xsim/ip/versal_cips_v3_2_0
|
||||
mipi_dphy_v4_3_4=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_4
|
||||
mult_gen_v12_0_18=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_18
|
||||
xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
|
||||
iomodule_v3_1_8=$RDI_DATADIR/xsim/ip/iomodule_v3_1_8
|
||||
util_ff_v1_0_0=$RDI_DATADIR/xsim/ip/util_ff_v1_0_0
|
||||
mem_tg_v1_0_8=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_8
|
||||
ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
|
||||
sim_trig_v1_0_7=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_7
|
||||
tmr_comparator_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_5
|
||||
pcie_dma_versal_v2_0_9=$RDI_DATADIR/xsim/ip/pcie_dma_versal_v2_0_9
|
||||
axi_ethernetlite_v3_0_25=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_25
|
||||
axi_memory_init_v1_0_7=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_7
|
||||
v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
|
||||
dft_v4_2_3=$RDI_DATADIR/xsim/ip/dft_v4_2_3
|
||||
qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0
|
||||
|
|
|
|||
Loading…
Reference in New Issue