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hardware runs on ddr3-1333! Now working on ddr3-1600

This commit is contained in:
AngeloJacobo 2025-01-19 17:15:40 +08:00
parent faa94a839a
commit 760979db27
7 changed files with 686 additions and 99 deletions
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17
example_demo/enclustra_kx2_st1/clk_wiz.v
View File

@ -6,14 +6,12 @@ module clk_wiz
output clk_out1,
output clk_out2,
output clk_out3,
output clk_out4,
input reset,
output locked
);
wire clk_out1_clk_wiz_0;
wire clk_out2_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clkfbout;
@ -22,20 +20,17 @@ module clk_wiz
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (5), // 200 MHz * 5 = 1000 MHz
.CLKFBOUT_MULT (10), // 200 MHz * 10 = 2000 MHz
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (12), // 1000 MHz / 12 = 83.333 MHz
.CLKOUT0_DIVIDE (12), // 2000 MHz / 12 = 166.67 MHz
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz
.CLKOUT1_DIVIDE (3), // 2000 MHz / 3 = 666.67 MHz
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (5), // 1000 MHz / 5 = 200 MHz
.CLKOUT2_DIVIDE (10), // 2000 MHz / 10 = 200 MHz
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DIVIDE (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (5) // 200 MHz input
)
plle2_adv_inst
@ -44,7 +39,6 @@ module clk_wiz
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT2 (clk_out3_clk_wiz_0),
.CLKOUT3 (clk_out4_clk_wiz_0),
.CLKFBIN (clkfbout),
.CLKIN1 (clk_in1),
.LOCKED (locked),
@ -59,8 +53,5 @@ module clk_wiz
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_clk_wiz_0));
BUFG clkout4_buf
(.O (clk_out4),
.I (clk_out4_clk_wiz_0));
endmodule

53
example_demo/enclustra_kx2_st1/enclustra_ddr3.v
View File

@ -110,25 +110,38 @@
end
wire clk_locked;
wire i_ddr3_clk_90;
clk_wiz clk_wiz_inst
// PLL
// clk_wiz clk_wiz_inst
// (
// // Clock out ports
// .clk_out1(i_controller_clk), // 166.67 Mhz
// .clk_out2(i_ddr3_clk), // 666.67 MHz
// .clk_out3(i_ref_clk), // 200 MHz
// // Status and control signals
// .reset(!i_rst_n),
// .locked(clk_locked),
// // Clock in ports
// .clk_in1(sys_clk_200MHz)
// );
// Clock Wizard
clk_wiz_0 clk_wiz_inst
(
// Clock out ports
.clk_out1(i_controller_clk), //83.333 Mhz
.clk_out2(i_ddr3_clk), // 333.333 MHz
.clk_out3(i_ref_clk), // 200 MHz
.clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90 degrees shift
// Status and control signals
.reset(!i_rst_n),
.locked(clk_locked),
// Clock in ports
.clk_in1(sys_clk_200MHz)
// Clock out ports
.controller_clk(i_controller_clk),
.ddr3_clk(i_ddr3_clk),
// Status and control signals
.reset(!i_rst_n),
.locked(clk_locked),
// Clock in ports
.clk_in1(sys_clk_200MHz)
);
// UART TX/RX module from https://github.com/ben-marshall/uart
uart_tx #(
.BIT_RATE(9600),
.CLK_HZ(83_333_333),
.CLK_HZ(200_000_000),
.PAYLOAD_BITS(8),
.STOP_BITS(1)
) uart_tx_inst (
@ -141,7 +154,7 @@
);
uart_rx #(
.BIT_RATE(9600),
.CLK_HZ(83_333_333),
.CLK_HZ(200_000_000),
.PAYLOAD_BITS(8),
.STOP_BITS(1)
) uart_rx_inst (
@ -173,8 +186,8 @@
// DDR3 Controller
ddr3_top #(
.CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.CONTROLLER_CLK_PERIOD(5_000), //ps, clock period of the controller interface
.DDR3_CLK_PERIOD(1_250), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD)
.ROW_BITS(15), //width of row address
.COL_BITS(10), //width of column address
.BA_BITS(3), //width of bank address
@ -192,8 +205,8 @@
//clock and reset
.i_controller_clk(i_controller_clk),
.i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD
.i_ref_clk(i_ref_clk),
.i_ddr3_clk_90(i_ddr3_clk_90),
.i_ref_clk(/*i_ref_clk*/sys_clk_200MHz),
.i_ddr3_clk_90(),
.i_rst_n(i_rst_n && clk_locked),
// Wishbone inputs
.i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
@ -236,9 +249,7 @@
.io_ddr3_dqs_n(ddr3_dqs_n),
.o_ddr3_dm(ddr3_dm),
.o_ddr3_odt(ddr3_odt), // on-die termination
.o_debug1(o_debug1),
.o_debug2(),
.o_debug3()
.o_debug1(o_debug1)
);
endmodule

30
rtl/ddr3_controller.v
View File

@ -1457,14 +1457,7 @@ module ddr3_controller #(
cmd_d[PRECHARGE_SLOT][10] = instruction[A10_CONTROL];
cmd_d[READ_SLOT][cmd_len-1-DUAL_RANK_DIMM:0] = {(!issue_read_command), CMD_RD[2:0] | {3{(!issue_read_command)}}, cmd_odt, cmd_ck_en, cmd_reset_n, {(ROW_BITS+BA_BITS){1'b0}}}; // issued during MPR reads (address does not matter)
cmd_d[ACTIVATE_SLOT][cmd_len-1-DUAL_RANK_DIMM:0] = {1'b0, 3'b111 , cmd_odt, cmd_ck_en, cmd_reset_n, {(ROW_BITS+BA_BITS){1'b0}}}; // always NOP by default
if(PRECHARGE_SLOT != 0) begin // if precharge slot is not the 0th slot, then all slots before precharge will have the previous value of cmd_ck_en
for(index = 0; index < PRECHARGE_SLOT; index=index+1) begin // slots before
if(DUAL_RANK_DIMM[0]) begin
cmd_d[index][CMD_CKE_2] = prev_cmd_ck_en[DUAL_RANK_DIMM];
end
cmd_d[index][CMD_CKE] = prev_cmd_ck_en[0];
end
end
// extra slot is created when READ and WRITE slots are the same
// this remaining slot should be NOP by default
if(WRITE_SLOT == READ_SLOT) begin
@ -1474,6 +1467,17 @@ module ddr3_controller #(
else begin
cmd_d[WRITE_SLOT][cmd_len-1-DUAL_RANK_DIMM:0] = {1'b0, 3'b111, cmd_odt, cmd_ck_en, cmd_reset_n, {(ROW_BITS+BA_BITS){1'b0}}}; // always NOP by default
end
// if precharge slot is not the 0th slot, then all slots before precharge will have the previous value of cmd_ck_en
if(PRECHARGE_SLOT != 0) begin
for(index = 0; index < PRECHARGE_SLOT; index=index+1) begin // slots before
if(DUAL_RANK_DIMM[0]) begin
cmd_d[index][CMD_CKE_2] = prev_cmd_ck_en[DUAL_RANK_DIMM];
end
cmd_d[index][CMD_CKE] = prev_cmd_ck_en[0];
end
end
/////////////////////////////////////////////////////////////////////////////////////////
// if dual rank is enabled, last 2 bits are {cs_2, cs_1}
if(DUAL_RANK_DIMM[0]) begin
@ -2378,7 +2382,7 @@ module ddr3_controller #(
if(sample_clk_repeat == REPEAT_CLK_SAMPLING) begin
sample_clk_repeat <= 0;
prev_write_level_feedback <= stored_write_level_feedback;
if(({prev_write_level_feedback, stored_write_level_feedback} == 2'b01) || write_level_fail[lane]) begin
if(({prev_write_level_feedback, stored_write_level_feedback} == 2'b01) /*|| write_level_fail[lane]*/) begin
/* verilator lint_on WIDTH */
/* verilator lint_off WIDTH */
if(lane == LANES - 1) begin
@ -2401,10 +2405,10 @@ module ddr3_controller #(
o_phy_odelay_data_ld[lane] <= 1;
o_phy_odelay_dqs_ld[lane] <= 1;
write_level_fail[lane] <= odelay_cntvalue_halfway;
if(odelay_cntvalue_halfway) begin // if halfway cntvalue is reached which is illegal (or impossible to happen), then we load the original cntvalues
odelay_data_cntvaluein[lane] <= DATA_INITIAL_ODELAY_TAP[4:0];
odelay_dqs_cntvaluein[lane] <= DQS_INITIAL_ODELAY_TAP[4:0];
end
// if(odelay_cntvalue_halfway) begin // if halfway cntvalue is reached which is illegal (or impossible to happen), then we load the original cntvalues
// odelay_data_cntvaluein[lane] <= DATA_INITIAL_ODELAY_TAP[4:0];
// odelay_dqs_cntvaluein[lane] <= DQS_INITIAL_ODELAY_TAP[4:0];
// end
state_calibrate <= START_WRITE_LEVEL;
end
end

4
testbench/ddr3.sv
View File

@ -94,9 +94,6 @@
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
`define den8192Mb
`define sg125
`define x16
`default_nettype wire
module ddr3 (
@ -117,6 +114,7 @@ module ddr3 (
tdqs_n,
odt
);
`include "sim_defines.vh"
`ifdef den1024Mb
`include "1024Mb_ddr3_parameters.vh"

15
testbench/ddr3_dimm_micron_sim.sv
View File

@ -27,16 +27,11 @@
////////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
`define den8192Mb
`define sg125
`define x16
//`define USE_CLOCK_WIZARD
`define TWO_LANES_x8
//`define EIGHT_LANES_x8
`define RAM_8Gb
`define XADC
//`define XADC
module ddr3_dimm_micron_sim;
`include "sim_defines.vh" // contains defines for simulation
`ifdef den1024Mb
`include "1024Mb_ddr3_parameters.vh"
`elsif den2048Mb
@ -62,8 +57,8 @@ module ddr3_dimm_micron_sim;
`endif
localparam CONTROLLER_CLK_PERIOD = 10_000, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 2500,//ps, period of clock input to DDR3 RAM device
localparam CONTROLLER_CLK_PERIOD = 5_000, //7_504, //ps, period of clock input to this DDR3 controller module
DDR3_CLK_PERIOD = 1250, //1_876,//ps, period of clock input to DDR3 RAM device
AUX_WIDTH = 16, // AUX lines
ECC_ENABLE = 0, // ECC enable
SELF_REFRESH = 2'b00,
@ -286,6 +281,8 @@ ddr3_top #(
.dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
.user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
);
`else
assign user_temp_alarm_out = 0;
`endif

642
testbench/ddr3_dimm_micron_sim_behav.wcfg
View File

@ -11,15 +11,20 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
<ZoomEndTime time="55.000001 us"></ZoomEndTime>
<Cursor1Time time="33.460000 us"></Cursor1Time>
<ZoomStartTime time="60.369478 us"></ZoomStartTime>
<ZoomEndTime time="168.769479 us"></ZoomEndTime>
<Cursor1Time time="150.702812 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="272"></NameColumnWidth>
<ValueColumnWidth column_width="125"></ValueColumnWidth>
<ValueColumnWidth column_width="113"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="52" />
<WVObjectSize size="69" />
<wave_markers>
<marker label="" time="37605000" />
<marker label="" time="37825000" />
<marker label="" time="35865000" />
</wave_markers>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Clocks and Reset</obj_property>
<obj_property name="DisplayName">label</obj_property>
@ -44,6 +49,14 @@
<obj_property name="ElementShortName">i_ref_clk</obj_property>
<obj_property name="ObjectShortName">i_ref_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_rst_n">
<obj_property name="ElementShortName">i_rst_n</obj_property>
<obj_property name="ObjectShortName">i_rst_n</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/sync_rst">
<obj_property name="ElementShortName">sync_rst</obj_property>
<obj_property name="ObjectShortName">sync_rst</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Self-refresh</obj_property>
<obj_property name="DisplayName">label</obj_property>
@ -56,9 +69,10 @@
<obj_property name="ElementShortName">user_self_refresh_q</obj_property>
<obj_property name="ObjectShortName">user_self_refresh_q</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/refresh_counter">
<obj_property name="ElementShortName">refresh_counter[8:0]</obj_property>
@ -73,14 +87,493 @@
<obj_property name="ElementShortName">i_wb_stb</obj_property>
<obj_property name="ObjectShortName">i_wb_stb</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/cmd_ck_en">
<obj_property name="ElementShortName">cmd_ck_en[0:0]</obj_property>
<obj_property name="ObjectShortName">cmd_ck_en[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/cmd_ck_en[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_cmd_ck_en">
<obj_property name="ElementShortName">prev_cmd_ck_en[0:0]</obj_property>
<obj_property name="ObjectShortName">prev_cmd_ck_en[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_cmd_ck_en[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FFA500</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd">
<obj_property name="ElementShortName">i_controller_cmd[103:0]</obj_property>
<obj_property name="ObjectShortName">i_controller_cmd[103:0]</obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[103]">
<obj_property name="ElementShortName">[103]</obj_property>
<obj_property name="ObjectShortName">[103]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[102]">
<obj_property name="ElementShortName">[102]</obj_property>
<obj_property name="ObjectShortName">[102]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[101]">
<obj_property name="ElementShortName">[101]</obj_property>
<obj_property name="ObjectShortName">[101]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[100]">
<obj_property name="ElementShortName">[100]</obj_property>
<obj_property name="ObjectShortName">[100]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[99]">
<obj_property name="ElementShortName">[99]</obj_property>
<obj_property name="ObjectShortName">[99]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[98]">
<obj_property name="ElementShortName">[98]</obj_property>
<obj_property name="ObjectShortName">[98]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[97]">
<obj_property name="ElementShortName">[97]</obj_property>
<obj_property name="ObjectShortName">[97]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[96]">
<obj_property name="ElementShortName">[96]</obj_property>
<obj_property name="ObjectShortName">[96]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[95]">
<obj_property name="ElementShortName">[95]</obj_property>
<obj_property name="ObjectShortName">[95]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[94]">
<obj_property name="ElementShortName">[94]</obj_property>
<obj_property name="ObjectShortName">[94]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[93]">
<obj_property name="ElementShortName">[93]</obj_property>
<obj_property name="ObjectShortName">[93]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[92]">
<obj_property name="ElementShortName">[92]</obj_property>
<obj_property name="ObjectShortName">[92]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[91]">
<obj_property name="ElementShortName">[91]</obj_property>
<obj_property name="ObjectShortName">[91]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[90]">
<obj_property name="ElementShortName">[90]</obj_property>
<obj_property name="ObjectShortName">[90]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[89]">
<obj_property name="ElementShortName">[89]</obj_property>
<obj_property name="ObjectShortName">[89]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[88]">
<obj_property name="ElementShortName">[88]</obj_property>
<obj_property name="ObjectShortName">[88]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[87]">
<obj_property name="ElementShortName">[87]</obj_property>
<obj_property name="ObjectShortName">[87]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[86]">
<obj_property name="ElementShortName">[86]</obj_property>
<obj_property name="ObjectShortName">[86]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[85]">
<obj_property name="ElementShortName">[85]</obj_property>
<obj_property name="ObjectShortName">[85]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[84]">
<obj_property name="ElementShortName">[84]</obj_property>
<obj_property name="ObjectShortName">[84]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[83]">
<obj_property name="ElementShortName">[83]</obj_property>
<obj_property name="ObjectShortName">[83]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[82]">
<obj_property name="ElementShortName">[82]</obj_property>
<obj_property name="ObjectShortName">[82]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[81]">
<obj_property name="ElementShortName">[81]</obj_property>
<obj_property name="ObjectShortName">[81]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[80]">
<obj_property name="ElementShortName">[80]</obj_property>
<obj_property name="ObjectShortName">[80]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[79]">
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<obj_property name="ObjectShortName">[5]</obj_property>
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<obj_property name="ObjectShortName">[4]</obj_property>
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<obj_property name="ObjectShortName">[1]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/i_controller_cmd[0]">
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<obj_property name="ObjectShortName">[0]</obj_property>
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</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">Calibration</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/odelay_cntvalue_halfway">
<obj_property name="ElementShortName">odelay_cntvalue_halfway</obj_property>
<obj_property name="ObjectShortName">odelay_cntvalue_halfway</obj_property>
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<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/write_level_fail">
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<obj_property name="ObjectShortName">write_level_fail[7:0]</obj_property>
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<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/prev_write_level_feedback">
<obj_property name="ElementShortName">prev_write_level_feedback</obj_property>
<obj_property name="ObjectShortName">prev_write_level_feedback</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/stored_write_level_feedback">
<obj_property name="ElementShortName">stored_write_level_feedback</obj_property>
<obj_property name="ObjectShortName">stored_write_level_feedback</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/sample_clk_repeat">
<obj_property name="ElementShortName">sample_clk_repeat[3:0]</obj_property>
<obj_property name="ObjectShortName">sample_clk_repeat[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/initial_calibration_done">
<obj_property name="ElementShortName">initial_calibration_done</obj_property>
<obj_property name="ObjectShortName">initial_calibration_done</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/state_calibrate">
<obj_property name="ElementShortName">state_calibrate[4:0]</obj_property>
<obj_property name="ObjectShortName">state_calibrate[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
<obj_property name="ObjectShortName">instruction_address[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/calibration_state">
<obj_property name="ElementShortName">calibration_state[319:0]</obj_property>
<obj_property name="ObjectShortName">calibration_state[319:0]</obj_property>
@ -93,26 +586,94 @@
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/o_phy_odelay_dqs_cntvaluein">
<obj_property name="ElementShortName">o_phy_odelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="ObjectShortName">o_phy_odelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/o_phy_idelay_dqs_cntvaluein">
<obj_property name="ElementShortName">o_phy_idelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="ObjectShortName">o_phy_idelay_dqs_cntvaluein[4:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/i_ddr3_clk">
<obj_property name="ElementShortName">i_ddr3_clk</obj_property>
<obj_property name="ObjectShortName">i_ddr3_clk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[15:0]</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_n">
<obj_property name="ElementShortName">o_ddr3_clk_n[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_clk_n[0:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_p">
<obj_property name="ElementShortName">o_ddr3_clk_p[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_clk_p[0:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_clk_p[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
<obj_property name="ElementShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[7]">
<obj_property name="ElementShortName">[7]</obj_property>
<obj_property name="ObjectShortName">[7]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[6]">
<obj_property name="ElementShortName">[6]</obj_property>
<obj_property name="ObjectShortName">[6]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[5]">
<obj_property name="ElementShortName">[5]</obj_property>
<obj_property name="ObjectShortName">[5]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[4]">
<obj_property name="ElementShortName">[4]</obj_property>
<obj_property name="ObjectShortName">[4]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[3]">
<obj_property name="ElementShortName">[3]</obj_property>
<obj_property name="ObjectShortName">[3]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[2]">
<obj_property name="ElementShortName">[2]</obj_property>
<obj_property name="ObjectShortName">[2]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[1]">
<obj_property name="ElementShortName">[1]</obj_property>
<obj_property name="ObjectShortName">[1]</obj_property>
<obj_property name="CustomSignalColor">#FFFF00</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs[0]">
<obj_property name="ElementShortName">[0]</obj_property>
<obj_property name="ObjectShortName">[0]</obj_property>
<obj_property name="CustomSignalColor">#FF0080</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
<obj_property name="ElementShortName">io_ddr3_dqs_n[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[63:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_phy_inst/idelay_dqs">
<obj_property name="ElementShortName">idelay_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">idelay_dqs[1:0]</obj_property>
<obj_property name="ElementShortName">idelay_dqs[7:0]</obj_property>
<obj_property name="ObjectShortName">idelay_dqs[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/lane">
<obj_property name="ElementShortName">lane[0:0]</obj_property>
<obj_property name="ObjectShortName">lane[0:0]</obj_property>
<obj_property name="ElementShortName">lane[2:0]</obj_property>
<obj_property name="ObjectShortName">lane[2:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/ddr3_controller_inst/instruction_address">
<obj_property name="ElementShortName">instruction_address[4:0]</obj_property>
@ -169,12 +730,12 @@
<obj_property name="ObjectShortName">i_wb_addr[25:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_data">
<obj_property name="ElementShortName">i_wb_data[127:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_data[127:0]</obj_property>
<obj_property name="ElementShortName">i_wb_data[511:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_data[511:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/i_wb_sel">
<obj_property name="ElementShortName">i_wb_sel[15:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_sel[15:0]</obj_property>
<obj_property name="ElementShortName">i_wb_sel[63:0]</obj_property>
<obj_property name="ObjectShortName">i_wb_sel[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_stall">
<obj_property name="ElementShortName">o_wb_stall</obj_property>
@ -185,20 +746,20 @@
<obj_property name="ObjectShortName">o_wb_ack</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_wb_data">
<obj_property name="ElementShortName">o_wb_data[127:0]</obj_property>
<obj_property name="ObjectShortName">o_wb_data[127:0]</obj_property>
<obj_property name="ElementShortName">o_wb_data[511:0]</obj_property>
<obj_property name="ObjectShortName">o_wb_data[511:0]</obj_property>
</wvobject>
<wvobject fp_name="divider869" type="divider">
<obj_property name="label">DDR3 Interface</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cke">
<obj_property name="ElementShortName">o_ddr3_cke[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cke[0:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cs_n">
<obj_property name="ElementShortName">o_ddr3_cs_n</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cs_n</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_cs_n">
<obj_property name="ElementShortName">o_ddr3_cs_n[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_cs_n[0:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_ras_n">
<obj_property name="ElementShortName">o_ddr3_ras_n</obj_property>
@ -221,23 +782,24 @@
<obj_property name="ObjectShortName">o_ddr3_ba_addr[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dq">
<obj_property name="ElementShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[15:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dq[63:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dq[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs">
<obj_property name="ElementShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[1:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs[7:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/io_ddr3_dqs_n">
<obj_property name="ElementShortName">io_ddr3_dqs_n[1:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[1:0]</obj_property>
<obj_property name="ElementShortName">io_ddr3_dqs_n[7:0]</obj_property>
<obj_property name="ObjectShortName">io_ddr3_dqs_n[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_dm">
<obj_property name="ElementShortName">o_ddr3_dm[1:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_dm[1:0]</obj_property>
<obj_property name="ElementShortName">o_ddr3_dm[7:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_dm[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_odt">
<obj_property name="ElementShortName">o_ddr3_odt</obj_property>
<obj_property name="ObjectShortName">o_ddr3_odt</obj_property>
<wvobject type="array" fp_name="/ddr3_dimm_micron_sim/ddr3_top/o_ddr3_odt">
<obj_property name="ElementShortName">o_ddr3_odt[0:0]</obj_property>
<obj_property name="ObjectShortName">o_ddr3_odt[0:0]</obj_property>
</wvobject>
</wave_config>

24
testbench/sim_defines.vh Normal file
View File

@ -0,0 +1,24 @@
// Define either TWO_LANES_x8 or EIGHT_LANES_x8
//`define TWO_LANES_x8
`define EIGHT_LANES_x8
`ifdef EIGHT_LANES_x8
`ifdef TWO_LANES_x8
ERROR: Display compilation error here
`endif
`define x8
`endif
`ifdef TWO_LANES_x8
`define x16
`endif
// Check if neither is defined
`ifndef EIGHT_LANES_x8
`ifndef TWO_LANES_x8
ERROR: Display compilation error here
`endif
`endif
`define den8192Mb
`define sg125