add new parameters, and links for OpenIPHub blog posts
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README.md
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README.md
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# Table of Contents
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- [Brief Description](https://github.com/AngeloJacobo/DDR3_Controller#brief-description)
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- [Open IP Hub Blog Posts](https://github.com/AngeloJacobo/UberDDR3/edit/main/README.md#open-ip-hub-blog-posts)
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- [Getting Started](https://github.com/AngeloJacobo/DDR3_Controller#getting-started)
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- [Instantiate Design](https://github.com/AngeloJacobo/DDR3_Controller#heavy_check_mark-instantiate-design)
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- [Create Constraint File](https://github.com/AngeloJacobo/DDR3_Controller#heavy_check_mark-create-constraint-file)
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- [Lint and Formal Verification](https://github.com/AngeloJacobo/DDR3_Controller#lint-and-formal-verification)
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- [Simulation](https://github.com/AngeloJacobo/DDR3_Controller#simulation)
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- [Demo Projects](https://github.com/AngeloJacobo/UberDDR3/tree/main?tab=readme-ov-file#demo-projects)
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- [Other Open-Sourced DDR3 Controllers](https://github.com/AngeloJacobo/DDR3_Controller#other-open-sourced-ddr3-controllers)
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- [Developer Documentation](https://github.com/AngeloJacobo/DDR3_Controller#developer-documentation)
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# Brief Description
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This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) for an 8-lane x8 DDR3 module running at 800 MHz DDR, but this is now being designed to be a more general DDR3 memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The user-interface is the basic Wishbone.
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This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) for an 8-lane x8 DDR3 module running at 800 MHz DDR, but this is now being designed to be a more general-purpose DDR3 memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The user-interface is the basic Wishbone. Optional features include:
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- AXI4 User Interface ([blog post here](https://www.openiphub.com/post/uberddr3-new-feature-axi4-interface))
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- SECDEC for error correction ([blog post here](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-1-post-5))
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- Self-Refresh ([blog post here](https://www.openiphub.com/post/uberddr3-self-refresh-reducing-power-consumption-in-idle-periods-post-9))
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- Dual-rank Support ([blog post here](https://www.openiphub.com/post/unlocking-more-memory-dual-rank-dimm-support-in-uberddr3-post-10))
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- Integratable with MicroBlaze ([blog post here](https://www.openiphub.com/post/uberddr3-microblaze-part-1-post-7))
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- Built-in self test
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This memory controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's calibration. The PHY's calibration handles the bitslip training, read-DQ/DQS alignment via MPR (read calibration), write-DQ/DQS alignment via write leveling (write calibration), and also an optional comprehensive read/write test.
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The optional comprehensive read/write tests made it easier to test the memory controller without needing an external CPU. These tests include a burst access, random access, and alternating read-write access tests. Only if no error is found on these tests will the calibration end and user can start accessing the wishbone interface.
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The optional built-in self read/write tests made it easier to test the memory controller without needing an external CPU. These tests include a burst access, random access, and alternating read-write access tests. Only if no error is found on these tests will the calibration end and user can start accessing the wishbone interface.
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This design is [formally verified](https://github.com/AngeloJacobo/DDR3_Controller#lint-and-formal-verification) and [simulated using the Micron DDR3 model](https://github.com/AngeloJacobo/DDR3_Controller#simulation).
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# Open IP Hub Blog Posts
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Check out these blog posts for detailed explanations on new features of UberDDR3, how to use them, and project demos:
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- [UberDDR3: An Opensource DDR3 Controller - Post #1](https://www.openiphub.com/post/uberddr3-an-opensource-ddr3-controller-post-1)
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- [Getting Started with UberDDR3 (Part 1) - Post #2](https://www.openiphub.com/post/getting-started-with-uberddr3-part-1-post-2)
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- [Getting Started with UberDDR3 (Part 2) - Post #3](https://www.openiphub.com/post/getting-started-with-uberddr3-part-2-post-3)
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- [UberDDR3 Update: AXI4 Interface - Post #4](https://www.openiphub.com/post/uberddr3-new-feature-axi4-interface)
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- [UberDDR3 Update: Error Correction (Part 1) - Post #5](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-1-post-5)
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- [UberDDR3 Feature Update: Error Correction (Part 2) - Post #6](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-2-post-6)
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- [UberDDR3 + MicroBlaze (Part 1) - Post #7](https://www.openiphub.com/post/uberddr3-microblaze-part-1-post-7)
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- [UberDDR3 + MicroBlaze (Part 2) - Post #8](https://www.openiphub.com/post/uberddr3-microblaze-part-2-post-8)
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- [UberDDR3 Self-Refresh: Reducing Power Consumption in Idle Periods - Post #9](https://www.openiphub.com/post/uberddr3-self-refresh-reducing-power-consumption-in-idle-periods-post-9)
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- [Unlocking More Memory: Dual-Rank DIMM Support in UberDDR3 - Post #10](https://www.openiphub.com/post/unlocking-more-memory-dual-rank-dimm-support-in-uberddr3-post-10)
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# Getting Started
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The recommended way to instantiate this IP is to use the top module [`rtl/ddr3_top.v`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/rtl/ddr3_top.v), a template for instantiation is also included in that file. Steps to include this DDR3 memory controller IP is to instantiate design, create the constraint file, then edit the localparams.
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@ -41,8 +59,12 @@ The first thing to edit are the **top-level parameters**:
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| MICRON_SIM | set to 1 if used in Micron DDR3 model to shorten power-on sequence, otherwise 0. |
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| ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0. <sup>[[3]](https://github.com/AngeloJacobo/DDR3_Controller#note) </sup> |
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| SECOND_WISHBONE | set to 1 if 2nd wishbone for debugging is needed , otherwise 0.|
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| WB_ERROR | set to 1 to support Wishbone error (asserts at ECC double bit error assuming ECCE_ENABLE != 0) |
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| SKIP_INTERNAL_TEST | set to 1 to skip built-in self test which usually takes > 2 seconds|
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| ECC_ENABLE | set to 0 to disable ECC OR: 1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC (more about [ECC on this blog post](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-1-post-5))|
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| DIC | Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change this when you know what you are doing) |
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| RTT_NOM | RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms) (only change when you know what you are doing) |
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| SELF_REFRESH | 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles (more on [self-refresh on this blog post](https://www.openiphub.com/post/uberddr3-self-refresh-reducing-power-consumption-in-idle-periods-post-9))|
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***
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After the parameters, connect the ports of the top module to your design. Below are the **ports for clocks and reset**:
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@ -197,7 +219,6 @@ The summary under `TEST CALIBRATION` are the results from the **internal** read/
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- The [QMTech Wukong demo project](./example_demo/qmtech_wukong) is just the same as the arty-s7 demo mentioned above.
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- To run this project on your [QMTech Wukong board](https://github.com/ChinaQMTECH/QM_XC7A100T_WUKONG_BOARD/tree/master/V3), import all verilog files and xdc file under `example_demo/qmtech_wukong/` and `rtl/`. Run synthesis-to-bitstream generation then upload the bitfile. After around 2 seconds, the 2 LEDS should light up then you can start interacting with the UART line. SW2 button is for reset.
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- Or just upload the [bitfile already given in the repo](./example_demo/qmtech_wukong).
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-
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- The [10Gb Ethernet Switch](https://github.com/ZipCPU/eth10g) project utilizes this DDR3 controller for accessing a single-rank DDR3 module (8 lanes of x8 DDR3) at DDR3-800 (100 MHz controller and 400 MHz PHY).
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# Other Open-Sourced DDR3 Controllers
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